dds.vo

直接数字频率合成器

	.devpor(devpor),
	.devoe(devoe),
	.dataout(\freword[8]~dataout ),
	.padio(freword[8]));
// synopsys translate_off
defparam \freword[8]~I .operation_mode = "input";
defparam \freword[8]~I .reg_source_mode = "none";
defparam \freword[8]~I .feedback_mode = "from_pin";
// synopsys translate_on

// atom is at LC5_B11
flex10ke_lcell \inst6|lpm_add_sub_component|adder|unreg_res_node[8]~I (
// Equation(s):
// \inst6|lpm_add_sub_component|adder|unreg_res_node[8]  = \freword[8]~dataout  $ \inst6|lpm_add_sub_component|adder|result_node|cout[7]  $ \inst|lpm_ff_component|dffs[8] 

	.dataa(vcc),
	.datab(\freword[8]~dataout ),
	.datac(vcc),
	.datad(\inst|lpm_ff_component|dffs[8] ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\inst6|lpm_add_sub_component|adder|result_node|cout[7] ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst6|lpm_add_sub_component|adder|unreg_res_node[8] ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst6|lpm_add_sub_component|adder|unreg_res_node[8]~I .operation_mode = "normal";
defparam \inst6|lpm_add_sub_component|adder|unreg_res_node[8]~I .cin_used = "true";
defparam \inst6|lpm_add_sub_component|adder|unreg_res_node[8]~I .packed_mode = "false";
defparam \inst6|lpm_add_sub_component|adder|unreg_res_node[8]~I .lut_mask = "C33C";
defparam \inst6|lpm_add_sub_component|adder|unreg_res_node[8]~I .clock_enable_mode = "false";
defparam \inst6|lpm_add_sub_component|adder|unreg_res_node[8]~I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC7_B11
flex10ke_lcell \inst|lpm_ff_component|dffs[8]~I (
// Equation(s):
// \inst|lpm_ff_component|dffs[8]  = DFFEA(\inst6|lpm_add_sub_component|adder|unreg_res_node[8] , GLOBAL(\clk~dataout ), , , , , )

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\inst6|lpm_add_sub_component|adder|unreg_res_node[8] ),
	.aclr(gnd),
	.aload(gnd),
	.clk(\clk~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst|lpm_ff_component|dffs[8] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst|lpm_ff_component|dffs[8]~I .operation_mode = "normal";
defparam \inst|lpm_ff_component|dffs[8]~I .packed_mode = "false";
defparam \inst|lpm_ff_component|dffs[8]~I .lut_mask = "FF00";
defparam \inst|lpm_ff_component|dffs[8]~I .clock_enable_mode = "false";
defparam \inst|lpm_ff_component|dffs[8]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC5_B12
flex10ke_lcell \inst4|lpm_add_sub_component|adder|unreg_res_node[8]~I (
// Equation(s):
// \inst4|lpm_add_sub_component|adder|unreg_res_node[8]  = \phase[8]~dataout  $ \inst4|lpm_add_sub_component|adder|result_node|cout[7]  $ \inst|lpm_ff_component|dffs[8] 

	.dataa(vcc),
	.datab(\phase[8]~dataout ),
	.datac(vcc),
	.datad(\inst|lpm_ff_component|dffs[8] ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\inst4|lpm_add_sub_component|adder|result_node|cout[7] ),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst4|lpm_add_sub_component|adder|unreg_res_node[8] ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \inst4|lpm_add_sub_component|adder|unreg_res_node[8]~I .operation_mode = "normal";
defparam \inst4|lpm_add_sub_component|adder|unreg_res_node[8]~I .cin_used = "true";
defparam \inst4|lpm_add_sub_component|adder|unreg_res_node[8]~I .packed_mode = "false";
defparam \inst4|lpm_add_sub_component|adder|unreg_res_node[8]~I .lut_mask = "C33C";
defparam \inst4|lpm_add_sub_component|adder|unreg_res_node[8]~I .clock_enable_mode = "false";
defparam \inst4|lpm_add_sub_component|adder|unreg_res_node[8]~I .output_mode = "comb_only";
// synopsys translate_on

// atom is at EC3_A
flex10ke_ram_slice \inst3|lpm_rom_component|srom|segment[0][9] (
	.datain(gnd),
	.clk0(\clk~dataout ),
	.clk1(gnd),
	.ena0(vcc),
	.ena1(vcc),
	.clr0(gnd),
	.we(),
	.re(vcc),
	.waddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
	.raddr({gnd,gnd,\inst4|lpm_add_sub_component|adder|unreg_res_node[8] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[7] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[6] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[5] ,
\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[4] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[3] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[2] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[1] ,
\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[0] }),
	.devclrn(devclrn),
	.devpor(devpor),
	.modesel(16'b0100000000010000),
	.dataout(\inst3|lpm_rom_component|srom|q[9] ));
// synopsys translate_off
defparam \inst3|lpm_rom_component|srom|segment[0][9] .operation_mode = "rom";
defparam \inst3|lpm_rom_component|srom|segment[0][9] .logical_ram_name = "lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|content";
defparam \inst3|lpm_rom_component|srom|segment[0][9] .init_file = "D:/5120.mif";
defparam \inst3|lpm_rom_component|srom|segment[0][9] .logical_ram_depth = 512;
defparam \inst3|lpm_rom_component|srom|segment[0][9] .logical_ram_width = 10;
defparam \inst3|lpm_rom_component|srom|segment[0][9] .address_width = 9;
defparam \inst3|lpm_rom_component|srom|segment[0][9] .first_address = 0;
defparam \inst3|lpm_rom_component|srom|segment[0][9] .last_address = 511;
defparam \inst3|lpm_rom_component|srom|segment[0][9] .bit_number = 9;
defparam \inst3|lpm_rom_component|srom|segment[0][9] .data_in_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][9] .data_in_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][9] .write_logic_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][9] .write_enable_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][9] .write_address_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][9] .read_enable_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][9] .read_enable_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][9] .read_address_clock = "clock0";
defparam \inst3|lpm_rom_component|srom|segment[0][9] .read_address_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][9] .data_out_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][9] .data_out_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][9] .mem1 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
// synopsys translate_on

// atom is at EC3_B
flex10ke_ram_slice \inst3|lpm_rom_component|srom|segment[0][8] (
	.datain(gnd),
	.clk0(\clk~dataout ),
	.clk1(gnd),
	.ena0(vcc),
	.ena1(vcc),
	.clr0(gnd),
	.we(),
	.re(vcc),
	.waddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
	.raddr({gnd,gnd,\inst4|lpm_add_sub_component|adder|unreg_res_node[8] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[7] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[6] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[5] ,
\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[4] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[3] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[2] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[1] ,
\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[0] }),
	.devclrn(devclrn),
	.devpor(devpor),
	.modesel(16'b0100000000010000),
	.dataout(\inst3|lpm_rom_component|srom|q[8] ));
// synopsys translate_off
defparam \inst3|lpm_rom_component|srom|segment[0][8] .operation_mode = "rom";
defparam \inst3|lpm_rom_component|srom|segment[0][8] .logical_ram_name = "lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|content";
defparam \inst3|lpm_rom_component|srom|segment[0][8] .init_file = "D:/5120.mif";
defparam \inst3|lpm_rom_component|srom|segment[0][8] .logical_ram_depth = 512;
defparam \inst3|lpm_rom_component|srom|segment[0][8] .logical_ram_width = 10;
defparam \inst3|lpm_rom_component|srom|segment[0][8] .address_width = 9;
defparam \inst3|lpm_rom_component|srom|segment[0][8] .first_address = 0;
defparam \inst3|lpm_rom_component|srom|segment[0][8] .last_address = 511;
defparam \inst3|lpm_rom_component|srom|segment[0][8] .bit_number = 8;
defparam \inst3|lpm_rom_component|srom|segment[0][8] .data_in_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][8] .data_in_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][8] .write_logic_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][8] .write_enable_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][8] .write_address_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][8] .read_enable_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][8] .read_enable_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][8] .read_address_clock = "clock0";
defparam \inst3|lpm_rom_component|srom|segment[0][8] .read_address_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][8] .data_out_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][8] .data_out_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][8] .mem1 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110;
// synopsys translate_on

// atom is at EC2_B
flex10ke_ram_slice \inst3|lpm_rom_component|srom|segment[0][7] (
	.datain(gnd),
	.clk0(\clk~dataout ),
	.clk1(gnd),
	.ena0(vcc),
	.ena1(vcc),
	.clr0(gnd),
	.we(),
	.re(vcc),
	.waddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
	.raddr({gnd,gnd,\inst4|lpm_add_sub_component|adder|unreg_res_node[8] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[7] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[6] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[5] ,
\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[4] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[3] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[2] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[1] ,
\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[0] }),
	.devclrn(devclrn),
	.devpor(devpor),
	.modesel(16'b0100000000010000),
	.dataout(\inst3|lpm_rom_component|srom|q[7] ));
// synopsys translate_off
defparam \inst3|lpm_rom_component|srom|segment[0][7] .operation_mode = "rom";
defparam \inst3|lpm_rom_component|srom|segment[0][7] .logical_ram_name = "lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|content";
defparam \inst3|lpm_rom_component|srom|segment[0][7] .init_file = "D:/5120.mif";
defparam \inst3|lpm_rom_component|srom|segment[0][7] .logical_ram_depth = 512;
defparam \inst3|lpm_rom_component|srom|segment[0][7] .logical_ram_width = 10;
defparam \inst3|lpm_rom_component|srom|segment[0][7] .address_width = 9;
defparam \inst3|lpm_rom_component|srom|segment[0][7] .first_address = 0;
defparam \inst3|lpm_rom_component|srom|segment[0][7] .last_address = 511;
defparam \inst3|lpm_rom_component|srom|segment[0][7] .bit_number = 7;
defparam \inst3|lpm_rom_component|srom|segment[0][7] .data_in_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][7] .data_in_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][7] .write_logic_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][7] .write_enable_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][7] .write_address_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][7] .read_enable_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][7] .read_enable_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][7] .read_address_clock = "clock0";
defparam \inst3|lpm_rom_component|srom|segment[0][7] .read_address_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][7] .data_out_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][7] .data_out_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][7] .mem1 = 512'b11111111111111111111111111111111111111111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111111111111111111111111111111111110000000000000000000000000000000000000000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000000000000000000000000000000000000000001;
// synopsys translate_on

// atom is at EC4_C
flex10ke_ram_slice \inst3|lpm_rom_component|srom|segment[0][6] (
	.datain(gnd),
	.clk0(\clk~dataout ),
	.clk1(gnd),
	.ena0(vcc),
	.ena1(vcc),
	.clr0(gnd),
	.we(),
	.re(vcc),
	.waddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
	.raddr({gnd,gnd,\inst4|lpm_add_sub_component|adder|unreg_res_node[8] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[7] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[6] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[5] ,
\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[4] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[3] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[2] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[1] ,
\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[0] }),
	.devclrn(devclrn),
	.devpor(devpor),
	.modesel(16'b0100000000010000),
	.dataout(\inst3|lpm_rom_component|srom|q[6] ));
// synopsys translate_off
defparam \inst3|lpm_rom_component|srom|segment[0][6] .operation_mode = "rom";
defparam \inst3|lpm_rom_component|srom|segment[0][6] .logical_ram_name = "lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|content";
defparam \inst3|lpm_rom_component|srom|segment[0][6] .init_file = "D:/5120.mif";
defparam \inst3|lpm_rom_component|srom|segment[0][6] .logical_ram_depth = 512;
defparam \inst3|lpm_rom_component|srom|segment[0][6] .logical_ram_width = 10;
defparam \inst3|lpm_rom_component|srom|segment[0][6] .address_width = 9;
defparam \inst3|lpm_rom_component|srom|segment[0][6] .first_address = 0;
defparam \inst3|lpm_rom_component|srom|segment[0][6] .last_address = 511;
defparam \inst3|lpm_rom_component|srom|segment[0][6] .bit_number = 6;
defparam \inst3|lpm_rom_component|srom|segment[0][6] .data_in_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][6] .data_in_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][6] .write_logic_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][6] .write_enable_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][6] .write_address_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][6] .read_enable_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][6] .read_enable_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][6] .read_address_clock = "clock0";
defparam \inst3|lpm_rom_component|srom|segment[0][6] .read_address_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][6] .data_out_clock = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][6] .data_out_clear = "none";
defparam \inst3|lpm_rom_component|srom|segment[0][6] .mem1 = 512'b11111111111111111111000000000000000000000011111111111111111111111111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111100000000000000000000001111111111111111111110000000000000000000001111111111111111111111000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000000000000000000000000011111111111111111111110000000000000000000001;
// synopsys translate_on

// atom is at EC1_C
flex10ke_ram_slice \inst3|lpm_rom_component|srom|segment[0][5] (
	.datain(gnd),
	.clk0(\clk~dataout ),
	.clk1(gnd),
	.ena0(vcc),
	.ena1(vcc),
	.clr0(gnd),
	.we(),
	.re(vcc),
	.waddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}),
	.raddr({gnd,gnd,\inst4|lpm_add_sub_component|adder|unreg_res_node[8] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[7] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[6] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[5] ,
\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[4] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[3] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[2] ,\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[1] ,
\inst4|lpm_add_sub_component|adder|result_node|cs_buffer[0] }),
	.devclrn(devclrn),
	.devpor(devpor),
	.modesel(16'b0100000000010000),
	.dataout(\inst3|lpm_rom_component|srom|q[5] ));
// synopsys translate_off
defparam \inst3|lpm_rom_component|srom|segment[0][5] .operation_mode = "rom";
defparam \inst3|lpm_rom_component|srom|segment[0][5] .logical_ram_name = "lpm_rom0:inst3|lpm_rom:lpm_rom_component|altrom:srom|content";
defparam \inst3|lpm_rom_component|srom|segment[0][5] .init_file = "D:/5120.mif";
defparam \inst3|lpm_rom_component|srom|segment[0][5] .logical_ram_depth = 512;
defparam \inst3|lpm_rom_component|srom|segment[0][5] .logical_ram_width = 10;
defparam \inst3|lpm_rom_component|srom|segment[0][5] .address_width = 9;
defparam \inst3|lpm_rom_component|srom|segment[0][5] .first_address = 0;
defparam \inst3|lpm_r