weifenqi.tan.qmsg

微分器：利用数字锁相环进行位同步信号提取的关键模块

{ "Info" "ITDB_TH_RESULT" "yicunqi:inst5\|inst codein clkin -3.007 ns register " "Info: th for register \"yicunqi:inst5\|inst\" (data pin = \"codein\", clock pin = \"clkin\") is -3.007 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 2.448 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to destination register is 2.448 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clkin 1 CLK PIN_17 10 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clkin'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "weifenqi.bdf" "" { Schematic "G:/Quartus/weifenqi/weifenqi.bdf" { { 224 -112 56 240 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.520 ns) + CELL(0.629 ns) 2.448 ns yicunqi:inst5\|inst 2 REG LC_X1_Y10_N7 1 " "Info: 2: + IC(0.520 ns) + CELL(0.629 ns) = 2.448 ns; Loc. = LC_X1_Y10_N7; Fanout = 1; REG Node = 'yicunqi:inst5\|inst'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.149 ns" { clkin yicunqi:inst5|inst } "NODE_NAME" } } { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 64 168 232 144 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 78.76 % ) " "Info: Total cell delay = 1.928 ns ( 78.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.520 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.520 ns ( 21.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { clkin yicunqi:inst5|inst } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { clkin clkin~out0 yicunqi:inst5|inst } { 0.000ns 0.000ns 0.520ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.013 ns + " "Info: + Micro hold delay of destination is 0.013 ns" {  } { { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 64 168 232 144 "inst" "" } } } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.468 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.468 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns codein 1 PIN PIN_7 2 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_7; Fanout = 2; PIN Node = 'codein'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { codein } "NODE_NAME" } } { "weifenqi.bdf" "" { Schematic "G:/Quartus/weifenqi/weifenqi.bdf" { { 184 -104 64 200 "codein" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.067 ns) + CELL(0.102 ns) 5.468 ns yicunqi:inst5\|inst 2 REG LC_X1_Y10_N7 1 " "Info: 2: + IC(4.067 ns) + CELL(0.102 ns) = 5.468 ns; Loc. = LC_X1_Y10_N7; Fanout = 1; REG Node = 'yicunqi:inst5\|inst'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.169 ns" { codein yicunqi:inst5|inst } "NODE_NAME" } } { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 64 168 232 144 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.401 ns ( 25.62 % ) " "Info: Total cell delay = 1.401 ns ( 25.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.067 ns ( 74.38 % ) " "Info: Total interconnect delay = 4.067 ns ( 74.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.468 ns" { codein yicunqi:inst5|inst } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.468 ns" { codein codein~out0 yicunqi:inst5|inst } { 0.000ns 0.000ns 4.067ns } { 0.000ns 1.299ns 0.102ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { clkin yicunqi:inst5|inst } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { clkin clkin~out0 yicunqi:inst5|inst } { 0.000ns 0.000ns 0.520ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.468 ns" { codein yicunqi:inst5|inst } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.468 ns" { codein codein~out0 yicunqi:inst5|inst } { 0.000ns 0.000ns 4.067ns } { 0.000ns 1.299ns 0.102ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 11 15:04:08 2008 " "Info: Processing ended: Sun May 11 15:04:08 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}