weifenqi.tan.qmsg

微分器：利用数字锁相环进行位同步信号提取的关键模块

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clkin register register yicunqi:inst5\|inst11 yicunqi:inst5\|inst12 320.1 MHz Internal " "Info: Clock \"clkin\" Internal fmax is restricted to 320.1 MHz between source register \"yicunqi:inst5\|inst11\" and destination register \"yicunqi:inst5\|inst12\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.562 ns 1.562 ns 3.124 ns " "Info: fmax restricted to Clock High delay (1.562 ns) plus Clock Low delay (1.562 ns) : restricted to 3.124 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.777 ns + Longest register register " "Info: + Longest register to register delay is 0.777 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns yicunqi:inst5\|inst11 1 REG LC_X1_Y10_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y10_N6; Fanout = 1; REG Node = 'yicunqi:inst5\|inst11'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { yicunqi:inst5|inst11 } "NODE_NAME" } } { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 200 408 472 280 "inst11" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.102 ns) 0.777 ns yicunqi:inst5\|inst12 2 REG LC_X1_Y10_N1 1 " "Info: 2: + IC(0.675 ns) + CELL(0.102 ns) = 0.777 ns; Loc. = LC_X1_Y10_N1; Fanout = 1; REG Node = 'yicunqi:inst5\|inst12'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.777 ns" { yicunqi:inst5|inst11 yicunqi:inst5|inst12 } "NODE_NAME" } } { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 200 488 552 280 "inst12" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.102 ns ( 13.13 % ) " "Info: Total cell delay = 0.102 ns ( 13.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.675 ns ( 86.87 % ) " "Info: Total interconnect delay = 0.675 ns ( 86.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.777 ns" { yicunqi:inst5|inst11 yicunqi:inst5|inst12 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.777 ns" { yicunqi:inst5|inst11 yicunqi:inst5|inst12 } { 0.000ns 0.675ns } { 0.000ns 0.102ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 2.448 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 2.448 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clkin 1 CLK PIN_17 10 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clkin'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "weifenqi.bdf" "" { Schematic "G:/Quartus/weifenqi/weifenqi.bdf" { { 224 -112 56 240 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.520 ns) + CELL(0.629 ns) 2.448 ns yicunqi:inst5\|inst12 2 REG LC_X1_Y10_N1 1 " "Info: 2: + IC(0.520 ns) + CELL(0.629 ns) = 2.448 ns; Loc. = LC_X1_Y10_N1; Fanout = 1; REG Node = 'yicunqi:inst5\|inst12'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.149 ns" { clkin yicunqi:inst5|inst12 } "NODE_NAME" } } { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 200 488 552 280 "inst12" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 78.76 % ) " "Info: Total cell delay = 1.928 ns ( 78.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.520 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.520 ns ( 21.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { clkin yicunqi:inst5|inst12 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { clkin clkin~out0 yicunqi:inst5|inst12 } { 0.000ns 0.000ns 0.520ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 2.448 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 2.448 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clkin 1 CLK PIN_17 10 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clkin'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "weifenqi.bdf" "" { Schematic "G:/Quartus/weifenqi/weifenqi.bdf" { { 224 -112 56 240 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.520 ns) + CELL(0.629 ns) 2.448 ns yicunqi:inst5\|inst11 2 REG LC_X1_Y10_N6 1 " "Info: 2: + IC(0.520 ns) + CELL(0.629 ns) = 2.448 ns; Loc. = LC_X1_Y10_N6; Fanout = 1; REG Node = 'yicunqi:inst5\|inst11'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.149 ns" { clkin yicunqi:inst5|inst11 } "NODE_NAME" } } { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 200 408 472 280 "inst11" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 78.76 % ) " "Info: Total cell delay = 1.928 ns ( 78.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.520 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.520 ns ( 21.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { clkin yicunqi:inst5|inst11 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { clkin clkin~out0 yicunqi:inst5|inst11 } { 0.000ns 0.000ns 0.520ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { clkin yicunqi:inst5|inst12 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { clkin clkin~out0 yicunqi:inst5|inst12 } { 0.000ns 0.000ns 0.520ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { clkin yicunqi:inst5|inst11 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { clkin clkin~out0 yicunqi:inst5|inst11 } { 0.000ns 0.000ns 0.520ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns + " "Info: + Micro clock to output delay of source is 0.198 ns" {  } { { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 200 408 472 280 "inst11" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns + " "Info: + Micro setup delay of destination is 0.033 ns" {  } { { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 200 488 552 280 "inst12" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.777 ns" { yicunqi:inst5|inst11 yicunqi:inst5|inst12 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.777 ns" { yicunqi:inst5|inst11 yicunqi:inst5|inst12 } { 0.000ns 0.675ns } { 0.000ns 0.102ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { clkin yicunqi:inst5|inst12 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { clkin clkin~out0 yicunqi:inst5|inst12 } { 0.000ns 0.000ns 0.520ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { clkin yicunqi:inst5|inst11 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { clkin clkin~out0 yicunqi:inst5|inst11 } { 0.000ns 0.000ns 0.520ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { yicunqi:inst5|inst12 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { yicunqi:inst5|inst12 } {  } {  } } } { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 200 488 552 280 "inst12" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "yicunqi:inst5\|inst codein clkin 3.053 ns register " "Info: tsu for register \"yicunqi:inst5\|inst\" (data pin = \"codein\", clock pin = \"clkin\") is 3.053 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.468 ns + Longest pin register " "Info: + Longest pin to register delay is 5.468 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns codein 1 PIN PIN_7 2 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_7; Fanout = 2; PIN Node = 'codein'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { codein } "NODE_NAME" } } { "weifenqi.bdf" "" { Schematic "G:/Quartus/weifenqi/weifenqi.bdf" { { 184 -104 64 200 "codein" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.067 ns) + CELL(0.102 ns) 5.468 ns yicunqi:inst5\|inst 2 REG LC_X1_Y10_N7 1 " "Info: 2: + IC(4.067 ns) + CELL(0.102 ns) = 5.468 ns; Loc. = LC_X1_Y10_N7; Fanout = 1; REG Node = 'yicunqi:inst5\|inst'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.169 ns" { codein yicunqi:inst5|inst } "NODE_NAME" } } { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 64 168 232 144 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.401 ns ( 25.62 % ) " "Info: Total cell delay = 1.401 ns ( 25.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.067 ns ( 74.38 % ) " "Info: Total interconnect delay = 4.067 ns ( 74.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.468 ns" { codein yicunqi:inst5|inst } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.468 ns" { codein codein~out0 yicunqi:inst5|inst } { 0.000ns 0.000ns 4.067ns } { 0.000ns 1.299ns 0.102ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.033 ns + " "Info: + Micro setup delay of destination is 0.033 ns" {  } { { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 64 168 232 144 "inst" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 2.448 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to destination register is 2.448 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clkin 1 CLK PIN_17 10 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clkin'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "weifenqi.bdf" "" { Schematic "G:/Quartus/weifenqi/weifenqi.bdf" { { 224 -112 56 240 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.520 ns) + CELL(0.629 ns) 2.448 ns yicunqi:inst5\|inst 2 REG LC_X1_Y10_N7 1 " "Info: 2: + IC(0.520 ns) + CELL(0.629 ns) = 2.448 ns; Loc. = LC_X1_Y10_N7; Fanout = 1; REG Node = 'yicunqi:inst5\|inst'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.149 ns" { clkin yicunqi:inst5|inst } "NODE_NAME" } } { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 64 168 232 144 "inst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 78.76 % ) " "Info: Total cell delay = 1.928 ns ( 78.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.520 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.520 ns ( 21.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { clkin yicunqi:inst5|inst } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { clkin clkin~out0 yicunqi:inst5|inst } { 0.000ns 0.000ns 0.520ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.468 ns" { codein yicunqi:inst5|inst } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.468 ns" { codein codein~out0 yicunqi:inst5|inst } { 0.000ns 0.000ns 4.067ns } { 0.000ns 1.299ns 0.102ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { clkin yicunqi:inst5|inst } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { clkin clkin~out0 yicunqi:inst5|inst } { 0.000ns 0.000ns 0.520ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkin codeout yicunqi:inst5\|inst12 5.822 ns register " "Info: tco from clock \"clkin\" to destination pin \"codeout\" through register \"yicunqi:inst5\|inst12\" is 5.822 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 2.448 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to source register is 2.448 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns clkin 1 CLK PIN_17 10 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clkin'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "weifenqi.bdf" "" { Schematic "G:/Quartus/weifenqi/weifenqi.bdf" { { 224 -112 56 240 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.520 ns) + CELL(0.629 ns) 2.448 ns yicunqi:inst5\|inst12 2 REG LC_X1_Y10_N1 1 " "Info: 2: + IC(0.520 ns) + CELL(0.629 ns) = 2.448 ns; Loc. = LC_X1_Y10_N1; Fanout = 1; REG Node = 'yicunqi:inst5\|inst12'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.149 ns" { clkin yicunqi:inst5|inst12 } "NODE_NAME" } } { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 200 488 552 280 "inst12" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns ( 78.76 % ) " "Info: Total cell delay = 1.928 ns ( 78.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.520 ns ( 21.24 % ) " "Info: Total interconnect delay = 0.520 ns ( 21.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { clkin yicunqi:inst5|inst12 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { clkin clkin~out0 yicunqi:inst5|inst12 } { 0.000ns 0.000ns 0.520ns } { 0.000ns 1.299ns 0.629ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.198 ns + " "Info: + Micro clock to output delay of source is 0.198 ns" {  } { { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 200 488 552 280 "inst12" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.176 ns + Longest register pin " "Info: + Longest register to pin delay is 3.176 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns yicunqi:inst5\|inst12 1 REG LC_X1_Y10_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y10_N1; Fanout = 1; REG Node = 'yicunqi:inst5\|inst12'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { yicunqi:inst5|inst12 } "NODE_NAME" } } { "yicunqi.bdf" "" { Schematic "G:/Quartus/weifenqi/yicunqi.bdf" { { 200 488 552 280 "inst12" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.334 ns) 0.334 ns inst1 2 COMB LC_X1_Y10_N1 1 " "Info: 2: + IC(0.000 ns) + CELL(0.334 ns) = 0.334 ns; Loc. = LC_X1_Y10_N1; Fanout = 1; COMB Node = 'inst1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.334 ns" { yicunqi:inst5|inst12 inst1 } "NODE_NAME" } } { "weifenqi.bdf" "" { Schematic "G:/Quartus/weifenqi/weifenqi.bdf" { { 104 400 464 152 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.963 ns) + CELL(1.879 ns) 3.176 ns codeout 3 PIN PIN_10 0 " "Info: 3: + IC(0.963 ns) + CELL(1.879 ns) = 3.176 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'codeout'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.842 ns" { inst1 codeout } "NODE_NAME" } } { "weifenqi.bdf" "" { Schematic "G:/Quartus/weifenqi/weifenqi.bdf" { { 120 504 680 136 "codeout" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.213 ns ( 69.68 % ) " "Info: Total cell delay = 2.213 ns ( 69.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.963 ns ( 30.32 % ) " "Info: Total interconnect delay = 0.963 ns ( 30.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.176 ns" { yicunqi:inst5|inst12 inst1 codeout } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.176 ns" { yicunqi:inst5|inst12 inst1 codeout } { 0.000ns 0.000ns 0.963ns } { 0.000ns 0.334ns 1.879ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.448 ns" { clkin yicunqi:inst5|inst12 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.448 ns" { clkin clkin~out0 yicunqi:inst5|inst12 } { 0.000ns 0.000ns 0.520ns } { 0.000ns 1.299ns 0.629ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.176 ns" { yicunqi:inst5|inst12 inst1 codeout } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.176 ns" { yicunqi:inst5|inst12 inst1 codeout } { 0.000ns 0.000ns 0.963ns } { 0.000ns 0.334ns 1.879ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "codein codeout 8.559 ns Longest " "Info: Longest tpd from source pin \"codein\" to destination pin \"codeout\" is 8.559 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.299 ns) 1.299 ns codein 1 PIN PIN_7 2 " "Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_7; Fanout = 2; PIN Node = 'codein'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { codein } "NODE_NAME" } } { "weifenqi.bdf" "" { Schematic "G:/Quartus/weifenqi/weifenqi.bdf" { { 184 -104 64 200 "codein" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.028 ns) + CELL(0.390 ns) 5.717 ns inst1 2 COMB LC_X1_Y10_N1 1 " "Info: 2: + IC(4.028 ns) + CELL(0.390 ns) = 5.717 ns; Loc. = LC_X1_Y10_N1; Fanout = 1; COMB Node = 'inst1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.418 ns" { codein inst1 } "NODE_NAME" } } { "weifenqi.bdf" "" { Schematic "G:/Quartus/weifenqi/weifenqi.bdf" { { 104 400 464 152 "inst1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.963 ns) + CELL(1.879 ns) 8.559 ns codeout 3 PIN PIN_10 0 " "Info: 3: + IC(0.963 ns) + CELL(1.879 ns) = 8.559 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'codeout'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.842 ns" { inst1 codeout } "NODE_NAME" } } { "weifenqi.bdf" "" { Schematic "G:/Quartus/weifenqi/weifenqi.bdf" { { 120 504 680 136 "codeout" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.568 ns ( 41.69 % ) " "Info: Total cell delay = 3.568 ns ( 41.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.991 ns ( 58.31 % ) " "Info: Total interconnect delay = 4.991 ns ( 58.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.559 ns" { codein inst1 codeout } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.559 ns" { codein codein~out0 inst1 codeout } { 0.000ns 0.000ns 4.028ns 0.963ns } { 0.000ns 1.299ns 0.390ns 1.879ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}