weifenqi.tan.rpt

微分器：利用数字锁相环进行位同步信号提取的关键模块

; N/A   ; None         ; 3.053 ns   ; codein ; yicunqi:inst5|inst ; clkin    ;
+-------+--------------+------------+--------+--------------------+----------+


+---------------------------------------------------------------------------------+
; tco                                                                             ;
+-------+--------------+------------+----------------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From                 ; To      ; From Clock ;
+-------+--------------+------------+----------------------+---------+------------+
; N/A   ; None         ; 5.822 ns   ; yicunqi:inst5|inst12 ; codeout ; clkin      ;
+-------+--------------+------------+----------------------+---------+------------+


+----------------------------------------------------------------+
; tpd                                                            ;
+-------+-------------------+-----------------+--------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From   ; To      ;
+-------+-------------------+-----------------+--------+---------+
; N/A   ; None              ; 8.559 ns        ; codein ; codeout ;
+-------+-------------------+-----------------+--------+---------+


+----------------------------------------------------------------------------------+
; th                                                                               ;
+---------------+-------------+-----------+--------+--------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To                 ; To Clock ;
+---------------+-------------+-----------+--------+--------------------+----------+
; N/A           ; None        ; -3.007 ns ; codein ; yicunqi:inst5|inst ; clkin    ;
+---------------+-------------+-----------+--------+--------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun May 11 15:04:06 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off weifenqi -c weifenqi --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clkin" is an undefined clock
Info: Clock "clkin" Internal fmax is restricted to 320.1 MHz between source register "yicunqi:inst5|inst11" and destination register "yicunqi:inst5|inst12"
    Info: fmax restricted to Clock High delay (1.562 ns) plus Clock Low delay (1.562 ns) : restricted to 3.124 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.777 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y10_N6; Fanout = 1; REG Node = 'yicunqi:inst5|inst11'
            Info: 2: + IC(0.675 ns) + CELL(0.102 ns) = 0.777 ns; Loc. = LC_X1_Y10_N1; Fanout = 1; REG Node = 'yicunqi:inst5|inst12'
            Info: Total cell delay = 0.102 ns ( 13.13 % )
            Info: Total interconnect delay = 0.675 ns ( 86.87 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clkin" to destination register is 2.448 ns
                Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clkin'
                Info: 2: + IC(0.520 ns) + CELL(0.629 ns) = 2.448 ns; Loc. = LC_X1_Y10_N1; Fanout = 1; REG Node = 'yicunqi:inst5|inst12'
                Info: Total cell delay = 1.928 ns ( 78.76 % )
                Info: Total interconnect delay = 0.520 ns ( 21.24 % )
            Info: - Longest clock path from clock "clkin" to source register is 2.448 ns
                Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clkin'
                Info: 2: + IC(0.520 ns) + CELL(0.629 ns) = 2.448 ns; Loc. = LC_X1_Y10_N6; Fanout = 1; REG Node = 'yicunqi:inst5|inst11'
                Info: Total cell delay = 1.928 ns ( 78.76 % )
                Info: Total interconnect delay = 0.520 ns ( 21.24 % )
        Info: + Micro clock to output delay of source is 0.198 ns
        Info: + Micro setup delay of destination is 0.033 ns
Info: tsu for register "yicunqi:inst5|inst" (data pin = "codein", clock pin = "clkin") is 3.053 ns
    Info: + Longest pin to register delay is 5.468 ns
        Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_7; Fanout = 2; PIN Node = 'codein'
        Info: 2: + IC(4.067 ns) + CELL(0.102 ns) = 5.468 ns; Loc. = LC_X1_Y10_N7; Fanout = 1; REG Node = 'yicunqi:inst5|inst'
        Info: Total cell delay = 1.401 ns ( 25.62 % )
        Info: Total interconnect delay = 4.067 ns ( 74.38 % )
    Info: + Micro setup delay of destination is 0.033 ns
    Info: - Shortest clock path from clock "clkin" to destination register is 2.448 ns
        Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clkin'
        Info: 2: + IC(0.520 ns) + CELL(0.629 ns) = 2.448 ns; Loc. = LC_X1_Y10_N7; Fanout = 1; REG Node = 'yicunqi:inst5|inst'
        Info: Total cell delay = 1.928 ns ( 78.76 % )
        Info: Total interconnect delay = 0.520 ns ( 21.24 % )
Info: tco from clock "clkin" to destination pin "codeout" through register "yicunqi:inst5|inst12" is 5.822 ns
    Info: + Longest clock path from clock "clkin" to source register is 2.448 ns
        Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clkin'
        Info: 2: + IC(0.520 ns) + CELL(0.629 ns) = 2.448 ns; Loc. = LC_X1_Y10_N1; Fanout = 1; REG Node = 'yicunqi:inst5|inst12'
        Info: Total cell delay = 1.928 ns ( 78.76 % )
        Info: Total interconnect delay = 0.520 ns ( 21.24 % )
    Info: + Micro clock to output delay of source is 0.198 ns
    Info: + Longest register to pin delay is 3.176 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y10_N1; Fanout = 1; REG Node = 'yicunqi:inst5|inst12'
        Info: 2: + IC(0.000 ns) + CELL(0.334 ns) = 0.334 ns; Loc. = LC_X1_Y10_N1; Fanout = 1; COMB Node = 'inst1'
        Info: 3: + IC(0.963 ns) + CELL(1.879 ns) = 3.176 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'codeout'
        Info: Total cell delay = 2.213 ns ( 69.68 % )
        Info: Total interconnect delay = 0.963 ns ( 30.32 % )
Info: Longest tpd from source pin "codein" to destination pin "codeout" is 8.559 ns
    Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_7; Fanout = 2; PIN Node = 'codein'
    Info: 2: + IC(4.028 ns) + CELL(0.390 ns) = 5.717 ns; Loc. = LC_X1_Y10_N1; Fanout = 1; COMB Node = 'inst1'
    Info: 3: + IC(0.963 ns) + CELL(1.879 ns) = 8.559 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'codeout'
    Info: Total cell delay = 3.568 ns ( 41.69 % )
    Info: Total interconnect delay = 4.991 ns ( 58.31 % )
Info: th for register "yicunqi:inst5|inst" (data pin = "codein", clock pin = "clkin") is -3.007 ns
    Info: + Longest clock path from clock "clkin" to destination register is 2.448 ns
        Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_17; Fanout = 10; CLK Node = 'clkin'
        Info: 2: + IC(0.520 ns) + CELL(0.629 ns) = 2.448 ns; Loc. = LC_X1_Y10_N7; Fanout = 1; REG Node = 'yicunqi:inst5|inst'
        Info: Total cell delay = 1.928 ns ( 78.76 % )
        Info: Total interconnect delay = 0.520 ns ( 21.24 % )
    Info: + Micro hold delay of destination is 0.013 ns
    Info: - Shortest pin to register delay is 5.468 ns
        Info: 1: + IC(0.000 ns) + CELL(1.299 ns) = 1.299 ns; Loc. = PIN_7; Fanout = 2; PIN Node = 'codein'
        Info: 2: + IC(4.067 ns) + CELL(0.102 ns) = 5.468 ns; Loc. = LC_X1_Y10_N7; Fanout = 1; REG Node = 'yicunqi:inst5|inst'
        Info: Total cell delay = 1.401 ns ( 25.62 % )
        Info: Total interconnect delay = 4.067 ns ( 74.38 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun May 11 15:04:08 2008
    Info: Elapsed time: 00:00:05