weifenqi.fit.rpt

微分器：利用数字锁相环进行位同步信号提取的关键模块

; LAB Logic Elements                                                        ;
+---------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 10.00) ; Number of LABs  (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 1                                           ; 0                           ;
; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 0                           ;
; 5                                           ; 0                           ;
; 6                                           ; 0                           ;
; 7                                           ; 0                           ;
; 8                                           ; 0                           ;
; 9                                           ; 0                           ;
; 10                                          ; 1                           ;
+---------------------------------------------+-----------------------------+


+------------------------------------------------------------------+
; LAB-wide Signals                                                 ;
+------------------------------------+-----------------------------+
; LAB-wide Signals  (Average = 1.00) ; Number of LABs  (Total = 1) ;
+------------------------------------+-----------------------------+
; 1 Clock                            ; 1                           ;
+------------------------------------+-----------------------------+


+----------------------------------------------------------------------------+
; LAB Signals Sourced                                                        ;
+----------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 10.00) ; Number of LABs  (Total = 1) ;
+----------------------------------------------+-----------------------------+
; 0                                            ; 0                           ;
; 1                                            ; 0                           ;
; 2                                            ; 0                           ;
; 3                                            ; 0                           ;
; 4                                            ; 0                           ;
; 5                                            ; 0                           ;
; 6                                            ; 0                           ;
; 7                                            ; 0                           ;
; 8                                            ; 0                           ;
; 9                                            ; 0                           ;
; 10                                           ; 1                           ;
+----------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 1.00) ; Number of LABs  (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 1                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 2.00) ; Number of LABs  (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun May 11 15:03:17 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off weifenqi -c weifenqi
Info: Selected device EP1C3T144I7 for design "weifenqi"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C3T144C7 is compatible
    Info: Device EP1C6T144C7 is compatible
    Info: Device EP1C6T144I7 is compatible
Info: No exact pin location assignment(s) for 3 pins of 3 total pins
    Info: Pin codeout not assigned to an exact location on the device
    Info: Pin codein not assigned to an exact location on the device
    Info: Pin clkin not assigned to an exact location on the device
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clkin" to use Global clock in PIN 17
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 2 (unused VREF, 3.30 VCCIO, 1 input, 1 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  19 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 0.777 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X1_Y10; Fanout = 1; REG Node = 'yicunqi:inst5|inst10'
    Info: 2: + IC(0.124 ns) + CELL(0.653 ns) = 0.777 ns; Loc. = LAB_X1_Y10; Fanout = 1; REG Node = 'yicunqi:inst5|inst11'
    Info: Total cell delay = 0.653 ns ( 84.04 % )
    Info: Total interconnect delay = 0.124 ns ( 15.96 % )
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Sun May 11 15:03:35 2008
    Info: Elapsed time: 00:00:19


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in G:/Quartus/weifenqi/weifenqi.fit.smsg.