alu.map.rpt

用verilog HDL代码编写的快速除法器

Analysis & Synthesis report for alu
Sun Jul 08 23:19:09 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Messages
  6. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Failed - Sun Jul 08 23:19:09 2007        ;
; Quartus II Version          ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name               ; alu                                      ;
; Top-level Entity Name       ; alu                                      ;
; Family                      ; FLEX10K                                  ;
+-----------------------------+------------------------------------------+


+----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                ;
+------------------------------------------------------------+-----------------+---------------+
; Option                                                     ; Setting         ; Default Value ;
+------------------------------------------------------------+-----------------+---------------+
; Device                                                     ; EPF10K10TC144-4 ;               ;
; Top-level entity name                                      ; alu             ; alu           ;
; Family name                                                ; FLEX10K         ; Stratix       ;
; Use smart compilation                                      ; Off             ; Off           ;
; Create Debugging Nodes for IP Cores                        ; Off             ; Off           ;
; Preserve fewer node names                                  ; On              ; On            ;
; Disable OpenCore Plus hardware evaluation                  ; Off             ; Off           ;
; Verilog Version                                            ; Verilog_2001    ; Verilog_2001  ;
; VHDL Version                                               ; VHDL93          ; VHDL93        ;
; State Machine Processing                                   ; Auto            ; Auto          ;
; Extract Verilog State Machines                             ; On              ; On            ;
; Extract VHDL State Machines                                ; On              ; On            ;
; Add Pass-Through Logic to Inferred RAMs                    ; On              ; On            ;
; NOT Gate Push-Back                                         ; On              ; On            ;
; Power-Up Don't Care                                        ; On              ; On            ;
; Remove Redundant Logic Cells                               ; Off             ; Off           ;
; Remove Duplicate Registers                                 ; On              ; On            ;
; Ignore CARRY Buffers                                       ; Off             ; Off           ;
; Ignore CASCADE Buffers                                     ; Off             ; Off           ;
; Ignore GLOBAL Buffers                                      ; Off             ; Off           ;
; Ignore ROW GLOBAL Buffers                                  ; Off             ; Off           ;
; Ignore LCELL Buffers                                       ; Off             ; Off           ;
; Ignore SOFT Buffers                                        ; On              ; On            ;
; Limit AHDL Integers to 32 Bits                             ; Off             ; Off           ;
; Auto Implement in ROM                                      ; Off             ; Off           ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K       ; Area            ; Area          ;
; Carry Chain Length -- FLEX 10K                             ; 32              ; 32            ;
; Cascade Chain Length                                       ; 2               ; 2             ;
; Auto Carry Chains                                          ; On              ; On            ;
; Auto Open-Drain Pins                                       ; On              ; On            ;
; Remove Duplicate Logic                                     ; On              ; On            ;
; Auto ROM Replacement                                       ; On              ; On            ;
; Auto RAM Replacement                                       ; On              ; On            ;
; Auto Clock Enable Replacement                              ; On              ; On            ;
; Auto Resource Sharing                                      ; Off             ; Off           ;
; Allow Any RAM Size For Recognition                         ; Off             ; Off           ;
; Allow Any ROM Size For Recognition                         ; Off             ; Off           ;
; Ignore translate_off and translate_on Synthesis Directives ; Off             ; Off           ;
; Show Parameter Settings Tables in Synthesis Report         ; On              ; On            ;
; HDL message level                                          ; Level2          ; Level2        ;
+------------------------------------------------------------+-----------------+---------------+


+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                        ;
+----------------------------------+-----------------+-----------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Jul 08 23:19:09 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off alu -c alu
Error (10170): Verilog HDL syntax error at alu.v(107) near text "(";  expecting ";", or "," File: F:/xf/alu-div/alu.v Line: 107
Error (10001): Verilog HDL or VHDL error at alu.v(107): declarations are illegal inside an unnamed block File: F:/xf/alu-div/alu.v Line: 107
Info (10151): Verilog HDL Declaration information at alu.v(107): "div" is declared here
Error (10112): Ignored module "alu" at alu.v(85) due to previous errors File: F:/xf/alu-div/alu.v Line: 85
Info: Found 0 design units, including 0 entities, in source file alu.v
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings
    Error: Processing ended: Sun Jul 08 23:19:09 2007
    Error: Elapsed time: 00:00:01


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in F:/xf/alu-div/alu.map.smsg.