📄 alu3.sim.vwf

📁 用verilog语言编写
💻 VWF
📖 第 1 页 / 共 2 页
字号:
上一页 12
			LEVEL 0 FOR 20.0;
			LEVEL 1 FOR 20.0;
		}
	}
}

TRANSITION_LIST("opcode[0]")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 50;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 10.0;
		}
	}
}

TRANSITION_LIST("out[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 12.5;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 30.0;
		}
		NODE
		{
			REPEAT = 5;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 20.0;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 40.0;
		}
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		NODE
		{
			REPEAT = 5;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 70.0;
		}
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 7.5;
	}
}

TRANSITION_LIST("out[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 22.5;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 10.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 20.0;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 30.0;
			LEVEL 1 FOR 20.0;
		}
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 20.0;
			LEVEL 0 FOR 30.0;
			LEVEL 1 FOR 20.0;
		}
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 20.0;
			LEVEL 0 FOR 40.0;
			LEVEL 1 FOR 10.0;
		}
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 40.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 7.5;
	}
}

TRANSITION_LIST("out[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 32.5;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 70.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 70.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 57.5;
	}
}

TRANSITION_LIST("out[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 12.5;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 50.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 20.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 30.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 30.0;
		LEVEL 0 FOR 40.0;
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 7.5;
	}
}

TRANSITION_LIST("out[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 12.5;
		NODE
		{
			REPEAT = 6;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 20.0;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 40.0;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 20.0;
			LEVEL 1 FOR 20.0;
			LEVEL 0 FOR 30.0;
		}
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 17.5;
	}
}

TRANSITION_LIST("out[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 12.5;
		NODE
		{
			REPEAT = 12;
			LEVEL 1 FOR 20.0;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 40.0;
		}
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 7.5;
	}
}

TRANSITION_LIST("out[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 22.5;
		NODE
		{
			REPEAT = 12;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 20.0;
			LEVEL 0 FOR 40.0;
		}
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 7.5;
	}
}

TRANSITION_LIST("out[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 32.5;
		NODE
		{
			REPEAT = 12;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 70.0;
		}
		LEVEL 1 FOR 7.5;
	}
}

DISPLAY_LINE
{
	CHANNEL = "clk";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "data1";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
	CHILDREN = 2, 3, 4, 5, 6, 7, 8, 9;
}

DISPLAY_LINE
{
	CHANNEL = "data1[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "data1[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "data1[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "data1[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "data1[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "data1[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "data1[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "data1[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "data2";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 10;
	TREE_LEVEL = 0;
	CHILDREN = 11, 12, 13, 14, 15, 16, 17, 18;
}

DISPLAY_LINE
{
	CHANNEL = "data2[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "data2[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "data2[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "data2[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 14;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "data2[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "data2[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "data2[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "data2[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 10;
}

DISPLAY_LINE
{
	CHANNEL = "opcode";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 19;
	TREE_LEVEL = 0;
	CHILDREN = 20, 21, 22;
}

DISPLAY_LINE
{
	CHANNEL = "opcode[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 19;
}

DISPLAY_LINE
{
	CHANNEL = "opcode[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 19;
}

DISPLAY_LINE
{
	CHANNEL = "opcode[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 22;
	TREE_LEVEL = 1;
	PARENT = 19;
}

DISPLAY_LINE
{
	CHANNEL = "out";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 23;
	TREE_LEVEL = 0;
	CHILDREN = 24, 25, 26, 27, 28, 29, 30, 31;
}

DISPLAY_LINE
{
	CHANNEL = "out[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 24;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "out[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 25;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "out[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 26;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "out[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 27;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "out[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 28;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "out[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 29;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "out[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 30;
	TREE_LEVEL = 1;
	PARENT = 23;
}

DISPLAY_LINE
{
	CHANNEL = "out[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 31;
	TREE_LEVEL = 1;
	PARENT = 23;
}

TIME_BAR
{
	TIME = 80000;
	MASTER = TRUE;
}
;
上一页 12
💿 文件大小 200 K
👤 上传用户 zhangtaoai007
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#verilog #语言 #编写
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -