alu3.hier_info

用verilog语言编写

|alu3
out[0] <= out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out[7] <= out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data1[0] => Add0.IN8
data1[0] => Add2.IN64
data1[0] => out~0.IN0
data1[0] => out~8.IN0
data1[0] => Selector7.IN7
data1[1] => Add0.IN7
data1[1] => Add2.IN63
data1[1] => out~1.IN0
data1[1] => out~9.IN0
data1[1] => Selector6.IN7
data1[2] => Add0.IN6
data1[2] => Add2.IN62
data1[2] => out~2.IN0
data1[2] => out~10.IN0
data1[2] => Selector5.IN7
data1[3] => Add0.IN5
data1[3] => Add2.IN61
data1[3] => out~3.IN0
data1[3] => out~11.IN0
data1[3] => Selector4.IN7
data1[4] => Add0.IN4
data1[4] => Add2.IN60
data1[4] => out~4.IN0
data1[4] => out~12.IN0
data1[4] => Selector3.IN7
data1[5] => Add0.IN3
data1[5] => Add2.IN59
data1[5] => out~5.IN0
data1[5] => out~13.IN0
data1[5] => Selector2.IN7
data1[6] => Add0.IN2
data1[6] => Add2.IN58
data1[6] => out~6.IN0
data1[6] => out~14.IN0
data1[6] => Selector1.IN7
data1[7] => Add0.IN1
data1[7] => Add2.IN57
data1[7] => out~7.IN0
data1[7] => out~15.IN0
data1[7] => Selector0.IN7
data2[0] => Add0.IN16
data2[0] => out~0.IN1
data2[0] => out~8.IN1
data2[0] => Add1.IN16
data2[1] => Add0.IN15
data2[1] => out~1.IN1
data2[1] => out~9.IN1
data2[1] => Add1.IN15
data2[2] => Add0.IN14
data2[2] => out~2.IN1
data2[2] => out~10.IN1
data2[2] => Add1.IN14
data2[3] => Add0.IN13
data2[3] => out~3.IN1
data2[3] => out~11.IN1
data2[3] => Add1.IN13
data2[4] => Add0.IN12
data2[4] => out~4.IN1
data2[4] => out~12.IN1
data2[4] => Add1.IN12
data2[5] => Add0.IN11
data2[5] => out~5.IN1
data2[5] => out~13.IN1
data2[5] => Add1.IN11
data2[6] => Add0.IN10
data2[6] => out~6.IN1
data2[6] => out~14.IN1
data2[6] => Add1.IN10
data2[7] => Add0.IN9
data2[7] => out~7.IN1
data2[7] => out~15.IN1
data2[7] => Add1.IN9
opcode[0] => Decoder0.IN2
opcode[1] => Decoder0.IN1
opcode[2] => Decoder0.IN0
clk => out[6]~reg0.CLK
clk => out[5]~reg0.CLK
clk => out[4]~reg0.CLK
clk => out[3]~reg0.CLK
clk => out[2]~reg0.CLK
clk => out[1]~reg0.CLK
clk => out[0]~reg0.CLK
clk => out[7]~reg0.CLK