add2.v

来自「两个4bit超前进位加法器实现8bit加法器」· Verilog 代码 · 共 18 行

module add1(x,y,sum,cout,cin);
input[3:0] x,y;
input cin;
output[3:0] sum;
output cout;
assign {cout,sum}=x+y+cin;
endmodule

module add2(a,b,s,co);
input[7:0] a,b;
wire ci;
output[7:0] s;
output co;

add1 a1(.x(a[3:0]),.y(b[3:0]),.sum(s[3:0]),.cout(ci),);
add1 a2(.x(a[7:4]),.y(b[7:4]),.sum(s[7:4]),.cout(co),.cin(ci));

endmodule