division.sim.rpt

来自「很实用的一个分频带码」· RPT 代码 · 共 380 行 · 第 1/5 页

+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      12.95 % ;
; Total nodes checked                                 ; 166          ;
; Total output ports checked                          ; 193          ;
; Total output ports with complete 1/0-value coverage ; 25           ;
; Total output ports with no 1/0-value coverage       ; 168          ;
; Total output ports with no 1-value coverage         ; 168          ;
; Total output ports with no 0-value coverage         ; 168          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                            ;
+----------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                        ; Output Port Name                                                                                 ; Output Port Type ;
+----------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------------+
; |division|any_odd:U5|clk1                                                        ; |division|any_odd:U5|clk1                                                                        ; data_out0        ;
; |division|any_odd:U5|clk2                                                        ; |division|any_odd:U5|clk2                                                                        ; data_out0        ;
; |division|clk_out~70                                                             ; |division|clk_out~70                                                                             ; data_out0        ;
; |division|any_odd:U5|LessThan~2254                                               ; |division|any_odd:U5|LessThan~2254                                                               ; data_out0        ;
; |division|any_odd:U5|LessThan~2261                                               ; |division|any_odd:U5|LessThan~2261                                                               ; data_out0        ;
; |division|any_odd:U5|LessThan~2268                                               ; |division|any_odd:U5|LessThan~2268                                                               ; data_out0        ;
; |division|any_odd:U5|LessThan~2272                                               ; |division|any_odd:U5|LessThan~2272                                                               ; data_out0        ;
; |division|any_odd:U5|lpm_counter:cout1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; |division|any_odd:U5|lpm_counter:cout1_rtl_0|alt_counter_f10ke:wysi_counter|q[1]                 ; data_out0        ;
; |division|any_odd:U5|lpm_counter:cout1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; |division|any_odd:U5|lpm_counter:cout1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT ; cout             ;
; |division|any_odd:U5|LessThan~2281                                               ; |division|any_odd:U5|LessThan~2281                                                               ; data_out0        ;
; |division|any_odd:U5|LessThan~2285                                               ; |division|any_odd:U5|LessThan~2285                                                               ; data_out0        ;
; |division|any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; |division|any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[1]                 ; data_out0        ;
; |division|any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; |division|any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT ; cout             ;
; |division|any_odd:U5|lpm_counter:cout1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; |division|any_odd:U5|lpm_counter:cout1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]                 ; data_out0        ;
; |division|any_odd:U5|lpm_counter:cout1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; |division|any_odd:U5|lpm_counter:cout1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT ; cout             ;
; |division|any_odd:U5|LessThan~2324                                               ; |division|any_odd:U5|LessThan~2324                                                               ; data_out0        ;
; |division|any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; |division|any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[0]                 ; data_out0        ;
; |division|any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; |division|any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT ; cout             ;
; |division|any_odd:U5|LessThan~2326                                               ; |division|any_odd:U5|LessThan~2326                                                               ; data_out0        ;
; |division|any_odd:U5|LessThan~2328                                               ; |division|any_odd:U5|LessThan~2328                                                               ; data_out0        ;
; |division|any_odd:U5|LessThan~2330                                               ; |division|any_odd:U5|LessThan~2330                                                               ; data_out0        ;
; |division|clk                                                                    ; |division|clk                                                                                    ; dataout          ;
; |division|clk_out                                                                ; |division|clk_out                                                                                ; padio            ;
; |division|clk_com                                                                ; |division|clk_com                                                                                ; padio            ;
; |division|clk_com~0                                                              ; |division|clk_com~0                                                                              ; data_out0        ;
+----------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                                 ;
+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                         ; Output Port Name                                                                                  ; Output Port Type ;
+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------+
; |division|decoder:u1|de[0]~232                                                                    ; |division|decoder:u1|de[0]~232                                                                    ; data_out0        ;
; |division|decoder:u1|de[1]~233                                                                    ; |division|decoder:u1|de[1]~233                                                                    ; data_out0        ;
; |division|decoder:u1|de[2]~234                                                                    ; |division|decoder:u1|de[2]~234                                                                    ; data_out0        ;
; |division|decoder:u1|de[3]~235                                                                    ; |division|decoder:u1|de[3]~235                                                                    ; data_out0        ;
; |division|decoder:u1|de[4]~236                                                                    ; |division|decoder:u1|de[4]~236                                                                    ; data_out0        ;
; |division|decoder:u1|de[5]~237                                                                    ; |division|decoder:u1|de[5]~237                                                                    ; data_out0        ;
; |division|decoder:u1|de[6]~238                                                                    ; |division|decoder:u1|de[6]~238                                                                    ; data_out0        ;
; |division|decoder:u2|de[0]~220                                                                    ; |division|decoder:u2|de[0]~220                                                                    ; data_out0        ;
; |division|decoder:u2|de[1]~221                                                                    ; |division|decoder:u2|de[1]~221                                                                    ; data_out0        ;
; |division|decoder:u2|de[2]~222                                                                    ; |division|decoder:u2|de[2]~222                                                                    ; data_out0        ;
; |division|decoder:u2|de[3]~223                                                                    ; |division|decoder:u2|de[3]~223                                                                    ; data_out0        ;
; |division|decoder:u2|de[4]~224                                                                    ; |division|decoder:u2|de[4]~224                                                                    ; data_out0        ;
; |division|decoder:u2|de[5]~225                                                                    ; |division|decoder:u2|de[5]~225                                                                    ; data_out0        ;
; |division|decoder:u2|de[6]~226                                                                    ; |division|decoder:u2|de[6]~226                                                                    ; data_out0        ;