any_odd.vhd

来自「很实用的一个分频带码」· VHDL 代码 · 共 45 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity any_odd is
generic (data_width : integer := 8);
port(input2 : in std_logic_vector(data_width - 1 downto 0);
  clk_in : in std_logic;
  clk_out : out std_logic);
end entity any_odd;

architecture div2 of any_odd is
signal cout1,cout2 : std_logic_vector(data_width - 1 downto 0);
signal clk1,clk2 : std_logic;
begin
process(clk_in)------rising edge
 begin
 if clk_in'event and clk_in='1' then
  if cout1 < (conv_integer(input2)-1) then
   cout1 <= cout1 + 1;
  else cout1 <= (others => '0');
  end if;
  if cout1 < (conv_integer(input2)-1)/2 then 
   clk1 <= '1';
  else clk1 <= '0';
  end if;
 end if;
end process;

---------------------------
process(clk_in)------falling edge
 begin
 if clk_in'event and clk_in='0' then
  if cout2 < (conv_integer(input2)-1) then
   cout2 <= cout2 + 1;
  else cout2 <= (others => '0');
  end if;
  if cout2 < (conv_integer(input2)-1)/2 then 
   clk2 <= '1';
  else clk2 <= '0';
  end if;
 end if;
end process;
clk_out <= clk1 or clk2;
end architecture div2;