decoder.vhd

来自「很实用的一个分频带码」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
entity decoder is
	port(bin : in std_logic_vector(2 downto 0);
		 de : out std_logic_vector(6 downto 0));
end entity;
----------------------------------------------------
architecture deco of decoder is
	begin
	process(bin)
	begin
	case bin is
		when "000" => de <= "0111111";---0
		when "001" => de <= "0000110";---1
		when "010" => de <= "1011011";---2
		when "011" => de <= "1001111";---3
		when "100" => de <= "1100110";---4
		when "101" => de <= "1101101";---5
		when "110" => de <= "1111101";---6
		when others => de <= "0000111";---7
		
	end case;
	end process;
end architecture;