division.map.qmsg

来自「很实用的一个分频带码」· QMSG 代码 · 共 27 行 · 第 1/3 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 22 14:02:23 2007 " "Info: Processing started: Thu Nov 22 14:02:23 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off division -c division " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off division -c division" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "division.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file division.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 division-freq " "Info: Found design unit 1: division-freq" {  } { { "division.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/division.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 division " "Info: Found entity 1: division" {  } { { "division.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/division.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "any_even.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file any_even.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 any_even-div1 " "Info: Found design unit 1: any_even-div1" {  } { { "any_even.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/any_even.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 any_even " "Info: Found entity 1: any_even" {  } { { "any_even.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/any_even.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "any_odd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file any_odd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 any_odd-div2 " "Info: Found design unit 1: any_odd-div2" {  } { { "any_odd.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/any_odd.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 any_odd " "Info: Found entity 1: any_odd" {  } { { "any_odd.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/any_odd.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder-deco " "Info: Found design unit 1: decoder-deco" {  } { { "decoder.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/decoder.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Info: Found entity 1: decoder" {  } { { "decoder.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/decoder.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "division " "Info: Elaborating entity \"division\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp1 division.vhd(44) " "Warning (10492): VHDL Process Statement warning at division.vhd(44): signal \"temp1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "division.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/division.vhd" 44 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}