division.tan.qmsg

很实用的一个分频带码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register any_odd:U5\|lpm_counter:cout2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[6\] register any_odd:U5\|lpm_counter:cout2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[7\] 47.17 MHz 21.2 ns Internal " "Info: Clock \"clk\" has Internal fmax of 47.17 MHz between source register \"any_odd:U5\|lpm_counter:cout2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[6\]\" and destination register \"any_odd:U5\|lpm_counter:cout2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[7\]\" (period= 21.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.600 ns + Longest register register " "Info: + Longest register to register delay is 17.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns any_odd:U5\|lpm_counter:cout2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[6\] 1 REG LC7_A13 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_A13; Fanout = 7; REG Node = 'any_odd:U5\|lpm_counter:cout2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "" { any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.300 ns) 4.600 ns any_odd:U5\|LessThan~2282 2 COMB LC2_A15 2 " "Info: 2: + IC(2.300 ns) + CELL(2.300 ns) = 4.600 ns; Loc. = LC2_A15; Fanout = 2; COMB Node = 'any_odd:U5\|LessThan~2282'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "4.600 ns" { any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[6] any_odd:U5|LessThan~2282 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 7.500 ns any_odd:U5\|LessThan~2283 3 COMB LC3_A15 2 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 7.500 ns; Loc. = LC3_A15; Fanout = 2; COMB Node = 'any_odd:U5\|LessThan~2283'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.900 ns" { any_odd:U5|LessThan~2282 any_odd:U5|LessThan~2283 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 9.800 ns any_odd:U5\|LessThan~2384 4 COMB LC7_A15 1 " "Info: 4: + IC(0.600 ns) + CELL(1.700 ns) = 9.800 ns; Loc. = LC7_A15; Fanout = 1; COMB Node = 'any_odd:U5\|LessThan~2384'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.300 ns" { any_odd:U5|LessThan~2283 any_odd:U5|LessThan~2384 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 11.300 ns any_odd:U5\|LessThan~2331 5 COMB LC8_A15 1 " "Info: 5: + IC(0.000 ns) + CELL(1.500 ns) = 11.300 ns; Loc. = LC8_A15; Fanout = 1; COMB Node = 'any_odd:U5\|LessThan~2331'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "1.500 ns" { any_odd:U5|LessThan~2384 any_odd:U5|LessThan~2331 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 13.700 ns any_odd:U5\|LessThan~2285 6 COMB LC1_A15 10 " "Info: 6: + IC(0.600 ns) + CELL(1.800 ns) = 13.700 ns; Loc. = LC1_A15; Fanout = 10; COMB Node = 'any_odd:U5\|LessThan~2285'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.400 ns" { any_odd:U5|LessThan~2331 any_odd:U5|LessThan~2285 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 17.600 ns any_odd:U5\|lpm_counter:cout2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[7\] 7 REG LC8_A13 5 " "Info: 7: + IC(2.200 ns) + CELL(1.700 ns) = 17.600 ns; Loc. = LC8_A13; Fanout = 5; REG Node = 'any_odd:U5\|lpm_counter:cout2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "3.900 ns" { any_odd:U5|LessThan~2285 any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.300 ns ( 64.20 % ) " "Info: Total cell delay = 11.300 ns ( 64.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.300 ns ( 35.80 % ) " "Info: Total interconnect delay = 6.300 ns ( 35.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "17.600 ns" { any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[6] any_odd:U5|LessThan~2282 any_odd:U5|LessThan~2283 any_odd:U5|LessThan~2384 any_odd:U5|LessThan~2331 any_odd:U5|LessThan~2285 any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "17.600 ns" { any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[6] any_odd:U5|LessThan~2282 any_odd:U5|LessThan~2283 any_odd:U5|LessThan~2384 any_odd:U5|LessThan~2331 any_odd:U5|LessThan~2285 any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 2.300ns 0.600ns 0.600ns 0.000ns 0.600ns 2.200ns } { 0.000ns 2.300ns 2.300ns 1.700ns 1.500ns 1.800ns 1.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_42 34 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_42; Fanout = 34; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "" { clk } "NODE_NAME" } "" } } { "division.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/division.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns any_odd:U5\|lpm_counter:cout2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[7\] 2 REG LC8_A13 5 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_A13; Fanout = 5; REG Node = 'any_odd:U5\|lpm_counter:cout2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.500 ns" { clk any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "5.300 ns" { clk any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_42 34 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_42; Fanout = 34; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "" { clk } "NODE_NAME" } "" } } { "division.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/division.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns any_odd:U5\|lpm_counter:cout2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[6\] 2 REG LC7_A13 7 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC7_A13; Fanout = 7; REG Node = 'any_odd:U5\|lpm_counter:cout2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.500 ns" { clk any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "5.300 ns" { clk any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "5.300 ns" { clk any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "5.300 ns" { clk any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "17.600 ns" { any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[6] any_odd:U5|LessThan~2282 any_odd:U5|LessThan~2283 any_odd:U5|LessThan~2384 any_odd:U5|LessThan~2331 any_odd:U5|LessThan~2285 any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "17.600 ns" { any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[6] any_odd:U5|LessThan~2282 any_odd:U5|LessThan~2283 any_odd:U5|LessThan~2384 any_odd:U5|LessThan~2331 any_odd:U5|LessThan~2285 any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 2.300ns 0.600ns 0.600ns 0.000ns 0.600ns 2.200ns } { 0.000ns 2.300ns 2.300ns 1.700ns 1.500ns 1.800ns 1.700ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "5.300 ns" { clk any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "5.300 ns" { clk any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out any_odd:U5|lpm_counter:cout2_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "any_odd:U5\|clk2 input\[0\] clk 74.200 ns register " "Info: tsu for register \"any_odd:U5\|clk2\" (data pin = \"input\[0\]\", clock pin = \"clk\") is 74.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "77.000 ns + Longest pin register " "Info: + Longest pin to register delay is 77.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns input\[0\] 1 PIN PIN_3 10 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_3; Fanout = 10; PIN Node = 'input\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "" { input[0] } "NODE_NAME" } "" } } { "division.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/division.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.900 ns) + CELL(1.800 ns) 9.200 ns any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~154 2 COMB LC2_C7 2 " "Info: 2: + IC(3.900 ns) + CELL(1.800 ns) = 9.200 ns; Loc. = LC2_C7; Fanout = 2; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~154'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "5.700 ns" { input[0] any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~154 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 11.600 ns any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\]~160 3 COMB LC6_C7 2 " "Info: 3: + IC(0.600 ns) + CELL(1.800 ns) = 11.600 ns; Loc. = LC6_C7; Fanout = 2; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\]~160'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.400 ns" { any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~154 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~160 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.800 ns) 16.100 ns any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~120 4 COMB LC5_C15 2 " "Info: 4: + IC(2.700 ns) + CELL(1.800 ns) = 16.100 ns; Loc. = LC5_C15; Fanout = 2; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~120'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "4.500 ns" { any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~160 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~120 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 18.500 ns any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~126 5 COMB LC4_C15 2 " "Info: 5: + IC(0.600 ns) + CELL(1.800 ns) = 18.500 ns; Loc. = LC4_C15; Fanout = 2; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~126'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.400 ns" { any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~120 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~126 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.800 ns) 23.000 ns any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[4\]~132 6 COMB LC5_C9 2 " "Info: 6: + IC(2.700 ns) + CELL(1.800 ns) = 23.000 ns; Loc. = LC5_C9; Fanout = 2; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[4\]~132'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "4.500 ns" { any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~126 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~132 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 25.400 ns any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[5\]~150 7 COMB LC2_C9 2 " "Info: 7: + IC(0.600 ns) + CELL(1.800 ns) = 25.400 ns; Loc. = LC2_C9; Fanout = 2; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[5\]~150'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.400 ns" { any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~132 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~150 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(1.800 ns) 30.900 ns any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[6\]~144 8 COMB LC2_A23 2 " "Info: 8: + IC(3.700 ns) + CELL(1.800 ns) = 30.900 ns; Loc. = LC2_A23; Fanout = 2; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[6\]~144'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "5.500 ns" { any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~150 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~144 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 33.300 ns any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\]~138 9 COMB LC6_A23 6 " "Info: 9: + IC(0.600 ns) + CELL(1.800 ns) = 33.300 ns; Loc. = LC6_A23; Fanout = 6; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\]~138'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.400 ns" { any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~144 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~138 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.400 ns) + CELL(2.300 ns) 40.000 ns any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~116 10 COMB LC6_C8 2 " "Info: 10: + IC(4.400 ns) + CELL(2.300 ns) = 40.000 ns; Loc. = LC6_C8; Fanout = 2; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~116'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "6.700 ns" { any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~138 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~116 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 42.400 ns any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\]~110 11 COMB LC4_C8 2 " "Info: 11: + IC(0.600 ns) + CELL(1.800 ns) = 42.400 ns; Loc. = LC4_C8; Fanout = 2; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\]~110'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.400 ns" { any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~116 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~110 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 44.800 ns any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~104 12 COMB LC3_C8 2 " "Info: 12: + IC(0.600 ns) + CELL(1.800 ns) = 44.800 ns; Loc. = LC3_C8; Fanout = 2; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~104'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.400 ns" { any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~110 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~104 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 47.200 ns any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~80 13 COMB LC1_C8 2 " "Info: 13: + IC(0.600 ns) + CELL(1.800 ns) = 47.200 ns; Loc. = LC1_C8; Fanout = 2; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~80'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.400 ns" { any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~104 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~80 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.800 ns) 51.400 ns any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[4\]~74 14 COMB LC2_C11 2 " "Info: 14: + IC(2.400 ns) + CELL(1.800 ns) = 51.400 ns; Loc. = LC2_C11; Fanout = 2; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[4\]~74'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "4.200 ns" { any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~80 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~74 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 53.800 ns any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[5\]~68 15 COMB LC4_C11 2 " "Info: 15: + IC(0.600 ns) + CELL(1.800 ns) = 53.800 ns; Loc. = LC4_C11; Fanout = 2; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[5\]~68'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.400 ns" { any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~74 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~68 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 57.800 ns any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[6\]~98 16 COMB LC7_C12 2 " "Info: 16: + IC(2.200 ns) + CELL(1.800 ns) = 57.800 ns; Loc. = LC7_C12; Fanout = 2; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[6\]~98'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "4.000 ns" { any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~68 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~98 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 60.200 ns any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\]~86 17 COMB LC4_C12 2 " "Info: 17: + IC(0.600 ns) + CELL(1.800 ns) = 60.200 ns; Loc. = LC4_C12; Fanout = 2; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[7\]~86'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.400 ns" { any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~98 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~86 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 62.600 ns any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[8\]~89 18 COMB LC2_C12 4 " "Info: 18: + IC(0.600 ns) + CELL(1.800 ns) = 62.600 ns; Loc. = LC2_C12; Fanout = 4; COMB Node = 'any_odd:U5\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[8\]~89'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.400 ns" { any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~86 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~89 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(2.300 ns) 68.500 ns any_odd:U5\|LessThan~2262 19 COMB LC2_A19 2 " "Info: 19: + IC(3.600 ns) + CELL(2.300 ns) = 68.500 ns; Loc. = LC2_A19; Fanout = 2; COMB Node = 'any_odd:U5\|LessThan~2262'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "5.900 ns" { any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~89 any_odd:U5|LessThan~2262 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 71.400 ns any_odd:U5\|LessThan~2263 20 COMB LC4_A19 2 " "Info: 20: + IC(0.600 ns) + CELL(2.300 ns) = 71.400 ns; Loc. = LC4_A19; Fanout = 2; COMB Node = 'any_odd:U5\|LessThan~2263'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.900 ns" { any_odd:U5|LessThan~2262 any_odd:U5|LessThan~2263 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 73.700 ns any_odd:U5\|LessThan~2370 21 COMB LC6_A19 1 " "Info: 21: + IC(0.600 ns) + CELL(1.700 ns) = 73.700 ns; Loc. = LC6_A19; Fanout = 1; COMB Node = 'any_odd:U5\|LessThan~2370'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.300 ns" { any_odd:U5|LessThan~2263 any_odd:U5|LessThan~2370 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 75.200 ns any_odd:U5\|LessThan~2327 22 COMB LC7_A19 1 " "Info: 22: + IC(0.000 ns) + CELL(1.500 ns) = 75.200 ns; Loc. = LC7_A19; Fanout = 1; COMB Node = 'any_odd:U5\|LessThan~2327'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "1.500 ns" { any_odd:U5|LessThan~2370 any_odd:U5|LessThan~2327 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 77.000 ns any_odd:U5\|clk2 23 REG LC1_A19 1 " "Info: 23: + IC(0.600 ns) + CELL(1.200 ns) = 77.000 ns; Loc. = LC1_A19; Fanout = 1; REG Node = 'any_odd:U5\|clk2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "1.800 ns" { any_odd:U5|LessThan~2327 any_odd:U5|clk2 } "NODE_NAME" } "" } } { "any_odd.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/any_odd.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "43.600 ns ( 56.62 % ) " "Info: Total cell delay = 43.600 ns ( 56.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "33.400 ns ( 43.38 % ) " "Info: Total interconnect delay = 33.400 ns ( 43.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "77.000 ns" { input[0] any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~154 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~160 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~120 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~126 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~132 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~150 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~144 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~138 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~116 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~110 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~104 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~80 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~74 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~68 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~98 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~86 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~89 any_odd:U5|LessThan~2262 any_odd:U5|LessThan~2263 any_odd:U5|LessThan~2370 any_odd:U5|LessThan~2327 any_odd:U5|clk2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "77.000 ns" { input[0] input[0]~out any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~154 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~160 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~120 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~126 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~132 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~150 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~144 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~138 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~116 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~110 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~104 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~80 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~74 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~68 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~98 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~86 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~89 any_odd:U5|LessThan~2262 any_odd:U5|LessThan~2263 any_odd:U5|LessThan~2370 any_odd:U5|LessThan~2327 any_odd:U5|clk2 } { 0.000ns 0.000ns 3.900ns 0.600ns 2.700ns 0.600ns 2.700ns 0.600ns 3.700ns 0.600ns 4.400ns 0.600ns 0.600ns 0.600ns 2.400ns 0.600ns 2.200ns 0.600ns 0.600ns 3.600ns 0.600ns 0.600ns 0.000ns 0.600ns } { 0.000ns 3.500ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 2.300ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 2.300ns 2.300ns 1.700ns 1.500ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "any_odd.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/any_odd.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_42 34 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_42; Fanout = 34; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "" { clk } "NODE_NAME" } "" } } { "division.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/division.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns any_odd:U5\|clk2 2 REG LC1_A19 1 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_A19; Fanout = 1; REG Node = 'any_odd:U5\|clk2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.500 ns" { clk any_odd:U5|clk2 } "NODE_NAME" } "" } } { "any_odd.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/any_odd.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "5.300 ns" { clk any_odd:U5|clk2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out any_odd:U5|clk2 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "77.000 ns" { input[0] any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~154 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~160 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~120 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~126 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~132 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~150 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~144 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~138 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~116 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~110 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~104 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~80 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~74 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~68 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~98 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~86 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~89 any_odd:U5|LessThan~2262 any_odd:U5|LessThan~2263 any_odd:U5|LessThan~2370 any_odd:U5|LessThan~2327 any_odd:U5|clk2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "77.000 ns" { input[0] input[0]~out any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~154 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~160 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~120 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~126 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~132 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~150 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~144 any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~138 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~116 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~110 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~104 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~80 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~74 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~68 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~98 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~86 any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~89 any_odd:U5|LessThan~2262 any_odd:U5|LessThan~2263 any_odd:U5|LessThan~2370 any_odd:U5|LessThan~2327 any_odd:U5|clk2 } { 0.000ns 0.000ns 3.900ns 0.600ns 2.700ns 0.600ns 2.700ns 0.600ns 3.700ns 0.600ns 4.400ns 0.600ns 0.600ns 0.600ns 2.400ns 0.600ns 2.200ns 0.600ns 0.600ns 3.600ns 0.600ns 0.600ns 0.000ns 0.600ns } { 0.000ns 3.500ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 2.300ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 1.800ns 2.300ns 2.300ns 1.700ns 1.500ns 1.200ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "5.300 ns" { clk any_odd:U5|clk2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out any_odd:U5|clk2 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clk_out any_odd:U5\|clk1 18.700 ns register " "Info: tco from clock \"clk\" to destination pin \"clk_out\" through register \"any_odd:U5\|clk1\" is 18.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_42 34 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_42; Fanout = 34; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "" { clk } "NODE_NAME" } "" } } { "division.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/division.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns any_odd:U5\|clk1 2 REG LC1_C2 1 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_C2; Fanout = 1; REG Node = 'any_odd:U5\|clk1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "2.500 ns" { clk any_odd:U5|clk1 } "NODE_NAME" } "" } } { "any_odd.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/any_odd.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "5.300 ns" { clk any_odd:U5|clk1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out any_odd:U5|clk1 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "any_odd.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/any_odd.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.300 ns + Longest register pin " "Info: + Longest register to pin delay is 12.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns any_odd:U5\|clk1 1 REG LC1_C2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C2; Fanout = 1; REG Node = 'any_odd:U5\|clk1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "" { any_odd:U5|clk1 } "NODE_NAME" } "" } } { "any_odd.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/any_odd.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(2.300 ns) 6.100 ns clk_out~70 2 COMB LC3_A19 1 " "Info: 2: + IC(3.800 ns) + CELL(2.300 ns) = 6.100 ns; Loc. = LC3_A19; Fanout = 1; COMB Node = 'clk_out~70'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "6.100 ns" { any_odd:U5|clk1 clk_out~70 } "NODE_NAME" } "" } } { "division.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/division.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(5.100 ns) 12.300 ns clk_out 3 PIN PIN_53 0 " "Info: 3: + IC(1.100 ns) + CELL(5.100 ns) = 12.300 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'clk_out'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "6.200 ns" { clk_out~70 clk_out } "NODE_NAME" } "" } } { "division.vhd" "" { Text "H:/实验程序of yys/EDA_design/division/division.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns ( 60.16 % ) " "Info: Total cell delay = 7.400 ns ( 60.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns ( 39.84 % ) " "Info: Total interconnect delay = 4.900 ns ( 39.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "12.300 ns" { any_odd:U5|clk1 clk_out~70 clk_out } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.300 ns" { any_odd:U5|clk1 clk_out~70 clk_out } { 0.000ns 3.800ns 1.100ns } { 0.000ns 2.300ns 5.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "5.300 ns" { clk any_odd:U5|clk1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out any_odd:U5|clk1 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "division" "UNKNOWN" "V1" "H:/实验程序of yys/EDA_design/division/db/division.quartus_db" { Floorplan "H:/实验程序of yys/EDA_design/division/" "" "12.300 ns" { any_odd:U5|clk1 clk_out~70 clk_out } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.300 ns" { any_odd:U5|clk1 clk_out~70 clk_out } { 0.000ns 3.800ns 1.100ns } { 0.000ns 2.300ns 5.100ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}