division.map.rpt

很实用的一个分频带码

; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                               ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                               ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                             ;
+------------------------+-------------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in H:/实验程序of yys/EDA_design/division/division.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Nov 22 14:02:23 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off division -c division
Info: Found 2 design units, including 1 entities, in source file division.vhd
    Info: Found design unit 1: division-freq
    Info: Found entity 1: division
Info: Found 2 design units, including 1 entities, in source file any_even.vhd
    Info: Found design unit 1: any_even-div1
    Info: Found entity 1: any_even
Info: Found 2 design units, including 1 entities, in source file any_odd.vhd
    Info: Found design unit 1: any_odd-div2
    Info: Found entity 1: any_odd
Info: Found 2 design units, including 1 entities, in source file decoder.vhd
    Info: Found design unit 1: decoder-deco
    Info: Found entity 1: decoder
Info: Elaborating entity "division" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at division.vhd(44): signal "temp1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at division.vhd(45): signal "temp2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "decoder" for hierarchy "decoder:u1"
Info: Elaborating entity "any_even" for hierarchy "any_even:u4"
Info: Elaborating entity "any_odd" for hierarchy "any_odd:U5"
Info: Inferred 3 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: "any_odd:U5|cout1[0]~8"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: "any_odd:U5|cout2[0]~8"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: "any_even:u4|coutQ[0]~8"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "led3[1]" stuck at VCC
Warning: Ignored 18 CARRY_SUM primitives
    Warning: Ignored 1 CARRY_SUM primitives -- cannot place fan-in logic in single logic cell
        Warning: Can't place logic feeding CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]" in single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~163" of type CARRY_SUM
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]" of type CARRY_SUM
    Warning: Ignored 17 CARRY_SUM primitive(s) -- cannot place fan-out logic in single logic cell
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~89" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~92" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~83" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~86" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~95" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~98" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~65" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~68" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~71" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~74" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~77" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~80" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~101" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~104" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~107" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~110" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~163" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~92" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~116" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~164" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~165" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~135" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~138" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~141" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~144" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~147" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~150" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~129" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~132" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~123" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~126" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~117" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~120" of type LUT
        Warning: Can't place logic fed by CARRY_SUM primitive "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]" into a single logic cell
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~157" of type LUT
            Warning: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~160" of type LUT
Info: Found the following redundant logic cells in design
    Info: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~154"
    Info: Node "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~152"
Info: Found the following redundant logic cells in design
    Info: Logic cell "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~152"
    Info: Logic cell "any_odd:U5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~154"
Info: Implemented 162 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 23 output pins
    Info: Implemented 130 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 61 warnings
    Info: Processing ended: Thu Nov 22 14:02:28 2007
    Info: Elapsed time: 00:00:05