clock.map.qmsg

一个用vhdl写的时钟代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 09 21:08:02 2008 " "Info: Processing started: Sun Mar 09 21:08:02 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count24.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file count24.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count24-behave " "Info: Found design unit 1: count24-behave" {  } { { "count24.vhd" "" { Text "E:/EDA/EDA_code/clock/count24.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 count24 " "Info: Found entity 1: count24" {  } { { "count24.vhd" "" { Text "E:/EDA/EDA_code/clock/count24.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock-behave " "Info: Found design unit 1: clock-behave" {  } { { "clock.vhd" "" { Text "E:/EDA/EDA_code/clock/clock.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.vhd" "" { Text "E:/EDA/EDA_code/clock/clock.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file count10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count10-behave " "Info: Found design unit 1: count10-behave" {  } { { "count10.vhd" "" { Text "E:/EDA/EDA_code/clock/count10.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 count10 " "Info: Found entity 1: count10" {  } { { "count10.vhd" "" { Text "E:/EDA/EDA_code/clock/count10.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count6.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file count6.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count6-behave " "Info: Found design unit 1: count6-behave" {  } { { "count6.vhd" "" { Text "E:/EDA/EDA_code/clock/count6.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 count6 " "Info: Found entity 1: count6" {  } { { "count6.vhd" "" { Text "E:/EDA/EDA_code/clock/count6.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder7s.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decoder7s.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder7s-behave " "Info: Found design unit 1: decoder7s-behave" {  } { { "decoder7s.vhd" "" { Text "E:/EDA/EDA_code/clock/decoder7s.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 decoder7s " "Info: Found entity 1: decoder7s" {  } { { "decoder7s.vhd" "" { Text "E:/EDA/EDA_code/clock/decoder7s.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "scan.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file scan.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 scan-behave " "Info: Found design unit 1: scan-behave" {  } { { "scan.vhd" "" { Text "E:/EDA/EDA_code/clock/scan.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 scan " "Info: Found entity 1: scan" {  } { { "scan.vhd" "" { Text "E:/EDA/EDA_code/clock/scan.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count12.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file count12.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count12-behave " "Info: Found design unit 1: count12-behave" {  } { { "count12.vhd" "" { Text "E:/EDA/EDA_code/clock/count12.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 count12 " "Info: Found entity 1: count12" {  } { { "count12.vhd" "" { Text "E:/EDA/EDA_code/clock/count12.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "timing.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file timing.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 timing-behave " "Info: Found design unit 1: timing-behave" {  } { { "timing.vhd" "" { Text "E:/EDA/EDA_code/clock/timing.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 timing " "Info: Found entity 1: timing" {  } { { "timing.vhd" "" { Text "E:/EDA/EDA_code/clock/timing.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "division.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file division.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 division-div1 " "Info: Found design unit 1: division-div1" {  } { { "division.vhd" "" { Text "E:/EDA/EDA_code/clock/division.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 division " "Info: Found entity 1: division" {  } { { "division.vhd" "" { Text "E:/EDA/EDA_code/clock/division.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg-behave " "Info: Found design unit 1: reg-behave" {  } { { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 reg " "Info: Found entity 1: reg" {  } { { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "reg " "Info: Elaborating entity \"reg\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "49 " "Info: Implemented 49 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "17 " "Info: Implemented 17 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "16 " "Info: Implemented 16 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 09 21:08:04 2008 " "Info: Processing ended: Sun Mar 09 21:08:04 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}