clock_hier_info

一个用vhdl写的时钟代码

|clock
clk_20m => division:U1.clk_in
rst => timing:U4.clr_time
rst => count6:U3.clr2
rst => count10:U2.clr1
clk_dis => scan:U6.clk_scan
alarm_set => reg:U8.lock
choose_mode => timing:U4.select12_24
set_min => i5.IN1
set_hou => timing:U4.setclk_h
display7[0] <= decoder7s:U7.bcd[0]
display7[1] <= decoder7s:U7.bcd[1]
display7[2] <= decoder7s:U7.bcd[2]
display7[3] <= decoder7s:U7.bcd[3]
display7[4] <= decoder7s:U7.bcd[4]
display7[5] <= decoder7s:U7.bcd[5]
display7[6] <= decoder7s:U7.bcd[6]
select6[0] <= scan:U6.choose[0]
select6[1] <= scan:U6.choose[1]
select6[2] <= scan:U6.choose[2]
select6[3] <= scan:U6.choose[3]
select6[4] <= scan:U6.choose[4]
select6[5] <= scan:U6.choose[5]


|clock|division:U1
clk_in => coutQ[30].CLK
clk_in => coutQ[29].CLK
clk_in => coutQ[28].CLK
clk_in => coutQ[27].CLK
clk_in => coutQ[26].CLK
clk_in => coutQ[25].CLK
clk_in => coutQ[24].CLK
clk_in => coutQ[23].CLK
clk_in => coutQ[22].CLK
clk_in => coutQ[21].CLK
clk_in => coutQ[20].CLK
clk_in => coutQ[19].CLK
clk_in => coutQ[18].CLK
clk_in => coutQ[17].CLK
clk_in => coutQ[16].CLK
clk_in => coutQ[15].CLK
clk_in => coutQ[14].CLK
clk_in => coutQ[13].CLK
clk_in => coutQ[12].CLK
clk_in => coutQ[11].CLK
clk_in => coutQ[10].CLK
clk_in => coutQ[9].CLK
clk_in => coutQ[8].CLK
clk_in => coutQ[7].CLK
clk_in => coutQ[6].CLK
clk_in => coutQ[5].CLK
clk_in => coutQ[4].CLK
clk_in => coutQ[3].CLK
clk_in => coutQ[2].CLK
clk_in => coutQ[1].CLK
clk_in => coutQ[0].CLK
clk_in => clk_outQ.CLK
clk_in => coutQ[31].CLK
clk_out <= clk_outQ.DB_MAX_OUTPUT_PORT_TYPE


|clock|count10:U2
clk1 => temp[2].CLK
clk1 => temp[1].CLK
clk1 => temp[0].CLK
clk1 => carry1~reg0.CLK
clk1 => temp[3].CLK
clr1 => temp[2].ACLR
clr1 => temp[1].ACLR
clr1 => temp[0].ACLR
clr1 => temp[3].ACLR
clr1 => carry1~reg0.ENA
carry1 <= carry1~reg0.DB_MAX_OUTPUT_PORT_TYPE
value1[0] <= temp[0].DB_MAX_OUTPUT_PORT_TYPE
value1[1] <= temp[1].DB_MAX_OUTPUT_PORT_TYPE
value1[2] <= temp[2].DB_MAX_OUTPUT_PORT_TYPE
value1[3] <= temp[3].DB_MAX_OUTPUT_PORT_TYPE


|clock|count6:U3
clk2 => temp[2].CLK
clk2 => temp[1].CLK
clk2 => temp[0].CLK
clk2 => carry2~reg0.CLK
clk2 => temp[3].CLK
clr2 => temp[2].ACLR
clr2 => temp[1].ACLR
clr2 => temp[0].ACLR
clr2 => temp[3].ACLR
clr2 => carry2~reg0.ENA
carry2 <= carry2~reg0.DB_MAX_OUTPUT_PORT_TYPE
value2[0] <= temp[0].DB_MAX_OUTPUT_PORT_TYPE
value2[1] <= temp[1].DB_MAX_OUTPUT_PORT_TYPE
value2[2] <= temp[2].DB_MAX_OUTPUT_PORT_TYPE
value2[3] <= temp[3].DB_MAX_OUTPUT_PORT_TYPE


|clock|timing:U4
clr_time => count24:U4.clr4
clr_time => count12:U3.clr3
clr_time => count6:U2.clr2
clr_time => count10:U1.clr1
setclk_h => i6.IN1
setclk_h => i7.IN1
setclk_m => count10:U1.clk1
select12_24 => i9.OUTPUTSELECT
select12_24 => i10.OUTPUTSELECT
select12_24 => i11.OUTPUTSELECT
select12_24 => i12.OUTPUTSELECT
select12_24 => i13.OUTPUTSELECT
select12_24 => i14.OUTPUTSELECT
select12_24 => i15.OUTPUTSELECT
select12_24 => i16.OUTPUTSELECT
data_min_l[0] <= count10:U1.value1[0]
data_min_l[1] <= count10:U1.value1[1]
data_min_l[2] <= count10:U1.value1[2]
data_min_l[3] <= count10:U1.value1[3]
data_min_h[0] <= count6:U2.value2[0]
data_min_h[1] <= count6:U2.value2[1]
data_min_h[2] <= count6:U2.value2[2]
data_min_h[3] <= count6:U2.value2[3]
data_hou_l[0] <= i12.DB_MAX_OUTPUT_PORT_TYPE
data_hou_l[1] <= i11.DB_MAX_OUTPUT_PORT_TYPE
data_hou_l[2] <= i10.DB_MAX_OUTPUT_PORT_TYPE
data_hou_l[3] <= i9.DB_MAX_OUTPUT_PORT_TYPE
data_hou_h[0] <= i16.DB_MAX_OUTPUT_PORT_TYPE
data_hou_h[1] <= i15.DB_MAX_OUTPUT_PORT_TYPE
data_hou_h[2] <= i14.DB_MAX_OUTPUT_PORT_TYPE
data_hou_h[3] <= i13.DB_MAX_OUTPUT_PORT_TYPE


|clock|timing:U4|count10:U1
clk1 => temp[2].CLK
clk1 => temp[1].CLK
clk1 => temp[0].CLK
clk1 => carry1~reg0.CLK
clk1 => temp[3].CLK
clr1 => temp[2].ACLR
clr1 => temp[1].ACLR
clr1 => temp[0].ACLR
clr1 => temp[3].ACLR
clr1 => carry1~reg0.ENA
carry1 <= carry1~reg0.DB_MAX_OUTPUT_PORT_TYPE
value1[0] <= temp[0].DB_MAX_OUTPUT_PORT_TYPE
value1[1] <= temp[1].DB_MAX_OUTPUT_PORT_TYPE
value1[2] <= temp[2].DB_MAX_OUTPUT_PORT_TYPE
value1[3] <= temp[3].DB_MAX_OUTPUT_PORT_TYPE


|clock|timing:U4|count6:U2
clk2 => temp[2].CLK
clk2 => temp[1].CLK
clk2 => temp[0].CLK
clk2 => carry2~reg0.CLK
clk2 => temp[3].CLK
clr2 => temp[2].ACLR
clr2 => temp[1].ACLR
clr2 => temp[0].ACLR
clr2 => temp[3].ACLR
clr2 => carry2~reg0.ENA
carry2 <= carry2~reg0.DB_MAX_OUTPUT_PORT_TYPE
value2[0] <= temp[0].DB_MAX_OUTPUT_PORT_TYPE
value2[1] <= temp[1].DB_MAX_OUTPUT_PORT_TYPE
value2[2] <= temp[2].DB_MAX_OUTPUT_PORT_TYPE
value2[3] <= temp[3].DB_MAX_OUTPUT_PORT_TYPE


|clock|timing:U4|count12:U3
clk3 => temp[2].CLK
clk3 => temp[1].CLK
clk3 => temp[0].CLK
clk3 => temp[3].CLK
clr3 => temp[2].ACLR
clr3 => temp[1].ACLR
clr3 => temp[0].ACLR
clr3 => temp[3].ACLR
value_l[0] <= i~5.DB_MAX_OUTPUT_PORT_TYPE
value_l[1] <= i~4.DB_MAX_OUTPUT_PORT_TYPE
value_l[2] <= i~3.DB_MAX_OUTPUT_PORT_TYPE
value_l[3] <= i~2.DB_MAX_OUTPUT_PORT_TYPE
value_h[0] <= i~9.DB_MAX_OUTPUT_PORT_TYPE
value_h[1] <= i~8.DB_MAX_OUTPUT_PORT_TYPE
value_h[2] <= i~7.DB_MAX_OUTPUT_PORT_TYPE
value_h[3] <= i~6.DB_MAX_OUTPUT_PORT_TYPE


|clock|timing:U4|count24:U4
clk4 => temp[3].CLK
clk4 => temp[2].CLK
clk4 => temp[1].CLK
clk4 => temp[0].CLK
clk4 => temp[4].CLK
clr4 => temp[3].ACLR
clr4 => temp[2].ACLR
clr4 => temp[1].ACLR
clr4 => temp[0].ACLR
clr4 => temp[4].ACLR
value_lb[0] <= i~5.DB_MAX_OUTPUT_PORT_TYPE
value_lb[1] <= i~4.DB_MAX_OUTPUT_PORT_TYPE
value_lb[2] <= i~3.DB_MAX_OUTPUT_PORT_TYPE
value_lb[3] <= i~2.DB_MAX_OUTPUT_PORT_TYPE
value_hb[0] <= i~9.DB_MAX_OUTPUT_PORT_TYPE
value_hb[1] <= i~8.DB_MAX_OUTPUT_PORT_TYPE
value_hb[2] <= i~7.DB_MAX_OUTPUT_PORT_TYPE
value_hb[3] <= i~6.DB_MAX_OUTPUT_PORT_TYPE


|clock|scan:U6
clk_scan => temp[1].CLK
clk_scan => temp[0].CLK
clk_scan => temp[2].CLK
data0[0] => i~5.IN0
data0[1] => i~4.IN0
data0[2] => i~3.IN0
data0[3] => i~2.IN0
data1[0] => i~5.IN1
data1[1] => i~4.IN1
data1[2] => i~3.IN1
data1[3] => i~2.IN1
data2[0] => i~5.IN2
data2[1] => i~4.IN2
data2[2] => i~3.IN2
data2[3] => i~2.IN2
data3[0] => i~5.IN3
data3[1] => i~4.IN3
data3[2] => i~3.IN3
data3[3] => i~2.IN3
data4[0] => i~5.IN4
data4[1] => i~4.IN4
data4[2] => i~3.IN4
data4[3] => i~2.IN4
data5[0] => i~5.IN5
data5[1] => i~4.IN5
data5[2] => i~3.IN5
data5[3] => i~2.IN5
dataout[0] <= i~5.DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= i~4.DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= i~3.DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= i~2.DB_MAX_OUTPUT_PORT_TYPE
choose[0] <= i~11.DB_MAX_OUTPUT_PORT_TYPE
choose[1] <= i~10.DB_MAX_OUTPUT_PORT_TYPE
choose[2] <= i~9.DB_MAX_OUTPUT_PORT_TYPE
choose[3] <= i~8.DB_MAX_OUTPUT_PORT_TYPE
choose[4] <= i~7.DB_MAX_OUTPUT_PORT_TYPE
choose[5] <= i~6.DB_MAX_OUTPUT_PORT_TYPE


|clock|decoder7s:U7
binary[0] => i~0.IN13
binary[0] => i~1.IN13
binary[0] => i~2.IN13
binary[0] => i~3.IN13
binary[0] => i~4.IN13
binary[0] => i~5.IN13
binary[0] => i~6.IN13
binary[1] => i~0.IN12
binary[1] => i~1.IN12
binary[1] => i~2.IN12
binary[1] => i~3.IN12
binary[1] => i~4.IN12
binary[1] => i~5.IN12
binary[1] => i~6.IN12
binary[2] => i~0.IN11
binary[2] => i~1.IN11
binary[2] => i~2.IN11
binary[2] => i~3.IN11
binary[2] => i~4.IN11
binary[2] => i~5.IN11
binary[2] => i~6.IN11
binary[3] => i~0.IN10
binary[3] => i~1.IN10
binary[3] => i~2.IN10
binary[3] => i~3.IN10
binary[3] => i~4.IN10
binary[3] => i~5.IN10
binary[3] => i~6.IN10
bcd[0] <= i~6.DB_MAX_OUTPUT_PORT_TYPE
bcd[1] <= i~5.DB_MAX_OUTPUT_PORT_TYPE
bcd[2] <= i~4.DB_MAX_OUTPUT_PORT_TYPE
bcd[3] <= i~3.DB_MAX_OUTPUT_PORT_TYPE
bcd[4] <= i~2.DB_MAX_OUTPUT_PORT_TYPE
bcd[5] <= i~1.DB_MAX_OUTPUT_PORT_TYPE
bcd[6] <= i~0.DB_MAX_OUTPUT_PORT_TYPE


|clock|reg:U8
lock => DataOut0[2]~reg0.CLK
lock => DataOut0[1]~reg0.CLK
lock => DataOut0[0]~reg0.CLK
lock => DataOut1[3]~reg0.CLK
lock => DataOut1[2]~reg0.CLK
lock => DataOut1[1]~reg0.CLK
lock => DataOut1[0]~reg0.CLK
lock => DataOut2[3]~reg0.CLK
lock => DataOut2[2]~reg0.CLK
lock => DataOut2[1]~reg0.CLK
lock => DataOut2[0]~reg0.CLK
lock => DataOut3[3]~reg0.CLK
lock => DataOut3[2]~reg0.CLK
lock => DataOut3[1]~reg0.CLK
lock => DataOut3[0]~reg0.CLK
lock => DataOut0[3]~reg0.CLK
DataIn0[0] => DataOut0[0]~reg0.DATAIN
DataIn0[1] => DataOut0[1]~reg0.DATAIN
DataIn0[2] => DataOut0[2]~reg0.DATAIN
DataIn0[3] => DataOut0[3]~reg0.DATAIN
DataIn1[0] => DataOut1[0]~reg0.DATAIN
DataIn1[1] => DataOut1[1]~reg0.DATAIN
DataIn1[2] => DataOut1[2]~reg0.DATAIN
DataIn1[3] => DataOut1[3]~reg0.DATAIN
DataIn2[0] => DataOut2[0]~reg0.DATAIN
DataIn2[1] => DataOut2[1]~reg0.DATAIN
DataIn2[2] => DataOut2[2]~reg0.DATAIN
DataIn2[3] => DataOut2[3]~reg0.DATAIN
DataIn3[0] => DataOut3[0]~reg0.DATAIN
DataIn3[1] => DataOut3[1]~reg0.DATAIN
DataIn3[2] => DataOut3[2]~reg0.DATAIN
DataIn3[3] => DataOut3[3]~reg0.DATAIN
DataOut0[0] <= DataOut0[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DataOut0[1] <= DataOut0[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DataOut0[2] <= DataOut0[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DataOut0[3] <= DataOut0[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DataOut1[0] <= DataOut1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DataOut1[1] <= DataOut1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DataOut1[2] <= DataOut1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DataOut1[3] <= DataOut1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DataOut2[0] <= DataOut2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DataOut2[1] <= DataOut2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DataOut2[2] <= DataOut2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DataOut2[3] <= DataOut2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DataOut3[0] <= DataOut3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DataOut3[1] <= DataOut3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DataOut3[2] <= DataOut3[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
DataOut3[3] <= DataOut3[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE