clock.tan.qmsg

一个用vhdl写的时钟代码

{ "Info" "ITAN_NO_REG2REG_EXIST" "lock " "Info: No valid register-to-register data paths exist for clock \"lock\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "DataOut1\[3\]~reg0 DataIn1\[3\] lock 4.100 ns register " "Info: tsu for register \"DataOut1\[3\]~reg0\" (data pin = \"DataIn1\[3\]\", clock pin = \"lock\") is 4.100 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.700 ns + Longest pin register " "Info: + Longest pin to register delay is 6.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns DataIn1\[3\] 1 PIN PIN_69 1 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_69; Fanout = 1; PIN Node = 'DataIn1\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "" { DataIn1[3] } "NODE_NAME" } "" } } { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(0.900 ns) 6.700 ns DataOut1\[3\]~reg0 2 REG LC1_A7 1 " "Info: 2: + IC(2.700 ns) + CELL(0.900 ns) = 6.700 ns; Loc. = LC1_A7; Fanout = 1; REG Node = 'DataOut1\[3\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "3.600 ns" { DataIn1[3] DataOut1[3]~reg0 } "NODE_NAME" } "" } } { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 59.70 % ) " "Info: Total cell delay = 4.000 ns ( 59.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 40.30 % ) " "Info: Total interconnect delay = 2.700 ns ( 40.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "6.700 ns" { DataIn1[3] DataOut1[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.700 ns" { DataIn1[3] DataIn1[3]~out DataOut1[3]~reg0 } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.100ns 0.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lock destination 3.900 ns - Shortest register " "Info: - Shortest clock path from clock \"lock\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns lock 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'lock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "" { lock } "NODE_NAME" } "" } } { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns DataOut1\[3\]~reg0 2 REG LC1_A7 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_A7; Fanout = 1; REG Node = 'DataOut1\[3\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "2.000 ns" { lock DataOut1[3]~reg0 } "NODE_NAME" } "" } } { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "3.900 ns" { lock DataOut1[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { lock lock~out DataOut1[3]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "6.700 ns" { DataIn1[3] DataOut1[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.700 ns" { DataIn1[3] DataIn1[3]~out DataOut1[3]~reg0 } { 0.000ns 0.000ns 2.700ns } { 0.000ns 3.100ns 0.900ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "3.900 ns" { lock DataOut1[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { lock lock~out DataOut1[3]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "lock DataOut3\[3\] DataOut3\[3\]~reg0 10.900 ns register " "Info: tco from clock \"lock\" to destination pin \"DataOut3\[3\]\" through register \"DataOut3\[3\]~reg0\" is 10.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lock source 3.900 ns + Longest register " "Info: + Longest clock path from clock \"lock\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns lock 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'lock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "" { lock } "NODE_NAME" } "" } } { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns DataOut3\[3\]~reg0 2 REG LC8_A16 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_A16; Fanout = 1; REG Node = 'DataOut3\[3\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "2.000 ns" { lock DataOut3[3]~reg0 } "NODE_NAME" } "" } } { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "3.900 ns" { lock DataOut3[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { lock lock~out DataOut3[3]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns + Longest register pin " "Info: + Longest register to pin delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DataOut3\[3\]~reg0 1 REG LC8_A16 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_A16; Fanout = 1; REG Node = 'DataOut3\[3\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "" { DataOut3[3]~reg0 } "NODE_NAME" } "" } } { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(3.900 ns) 6.100 ns DataOut3\[3\] 2 PIN PIN_70 0 " "Info: 2: + IC(2.200 ns) + CELL(3.900 ns) = 6.100 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'DataOut3\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "6.100 ns" { DataOut3[3]~reg0 DataOut3[3] } "NODE_NAME" } "" } } { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 63.93 % ) " "Info: Total cell delay = 3.900 ns ( 63.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns ( 36.07 % ) " "Info: Total interconnect delay = 2.200 ns ( 36.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "6.100 ns" { DataOut3[3]~reg0 DataOut3[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.100 ns" { DataOut3[3]~reg0 DataOut3[3] } { 0.000ns 2.200ns } { 0.000ns 3.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "3.900 ns" { lock DataOut3[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { lock lock~out DataOut3[3]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "6.100 ns" { DataOut3[3]~reg0 DataOut3[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.100 ns" { DataOut3[3]~reg0 DataOut3[3] } { 0.000ns 2.200ns } { 0.000ns 3.900ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "DataOut0\[2\]~reg0 DataIn0\[2\] lock 1.000 ns register " "Info: th for register \"DataOut0\[2\]~reg0\" (data pin = \"DataIn0\[2\]\", clock pin = \"lock\") is 1.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "lock destination 3.900 ns + Longest register " "Info: + Longest clock path from clock \"lock\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns lock 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'lock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "" { lock } "NODE_NAME" } "" } } { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns DataOut0\[2\]~reg0 2 REG LC7_C23 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC7_C23; Fanout = 1; REG Node = 'DataOut0\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "2.000 ns" { lock DataOut0[2]~reg0 } "NODE_NAME" } "" } } { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "3.900 ns" { lock DataOut0[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { lock lock~out DataOut0[2]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.400 ns + " "Info: + Micro hold delay of destination is 1.400 ns" {  } { { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.300 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns DataIn0\[2\] 1 PIN PIN_44 1 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_44; Fanout = 1; PIN Node = 'DataIn0\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "" { DataIn0[2] } "NODE_NAME" } "" } } { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(0.900 ns) 4.300 ns DataOut0\[2\]~reg0 2 REG LC7_C23 1 " "Info: 2: + IC(1.500 ns) + CELL(0.900 ns) = 4.300 ns; Loc. = LC7_C23; Fanout = 1; REG Node = 'DataOut0\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "2.400 ns" { DataIn0[2] DataOut0[2]~reg0 } "NODE_NAME" } "" } } { "reg.vhd" "" { Text "E:/EDA/EDA_code/clock/reg.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 65.12 % ) " "Info: Total cell delay = 2.800 ns ( 65.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 34.88 % ) " "Info: Total interconnect delay = 1.500 ns ( 34.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "4.300 ns" { DataIn0[2] DataOut0[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.300 ns" { DataIn0[2] DataIn0[2]~out DataOut0[2]~reg0 } { 0.000ns 0.000ns 1.500ns } { 0.000ns 1.900ns 0.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "3.900 ns" { lock DataOut0[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.900 ns" { lock lock~out DataOut0[2]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "E:/EDA/EDA_code/clock/db/clock.quartus_db" { Floorplan "E:/EDA/EDA_code/clock/" "" "4.300 ns" { DataIn0[2] DataOut0[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.300 ns" { DataIn0[2] DataIn0[2]~out DataOut0[2]~reg0 } { 0.000ns 0.000ns 1.500ns } { 0.000ns 1.900ns 0.900ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 09 21:08:14 2008 " "Info: Processing ended: Sun Mar 09 21:08:14 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}