clock.tan.rpt

一个用vhdl写的时钟代码

+---------------------------------------------------------------------------------+
; tco                                                                             ;
+-------+--------------+------------+------------------+-------------+------------+
; Slack ; Required tco ; Actual tco ; From             ; To          ; From Clock ;
+-------+--------------+------------+------------------+-------------+------------+
; N/A   ; None         ; 10.900 ns  ; DataOut3[3]~reg0 ; DataOut3[3] ; lock       ;
; N/A   ; None         ; 10.900 ns  ; DataOut3[1]~reg0 ; DataOut3[1] ; lock       ;
; N/A   ; None         ; 10.900 ns  ; DataOut3[0]~reg0 ; DataOut3[0] ; lock       ;
; N/A   ; None         ; 10.900 ns  ; DataOut2[1]~reg0 ; DataOut2[1] ; lock       ;
; N/A   ; None         ; 10.000 ns  ; DataOut2[2]~reg0 ; DataOut2[2] ; lock       ;
; N/A   ; None         ; 9.900 ns   ; DataOut3[2]~reg0 ; DataOut3[2] ; lock       ;
; N/A   ; None         ; 9.900 ns   ; DataOut2[3]~reg0 ; DataOut2[3] ; lock       ;
; N/A   ; None         ; 9.900 ns   ; DataOut2[0]~reg0 ; DataOut2[0] ; lock       ;
; N/A   ; None         ; 9.900 ns   ; DataOut1[3]~reg0 ; DataOut1[3] ; lock       ;
; N/A   ; None         ; 9.900 ns   ; DataOut1[2]~reg0 ; DataOut1[2] ; lock       ;
; N/A   ; None         ; 9.900 ns   ; DataOut1[1]~reg0 ; DataOut1[1] ; lock       ;
; N/A   ; None         ; 9.900 ns   ; DataOut1[0]~reg0 ; DataOut1[0] ; lock       ;
; N/A   ; None         ; 9.900 ns   ; DataOut0[3]~reg0 ; DataOut0[3] ; lock       ;
; N/A   ; None         ; 9.900 ns   ; DataOut0[2]~reg0 ; DataOut0[2] ; lock       ;
; N/A   ; None         ; 9.900 ns   ; DataOut0[1]~reg0 ; DataOut0[1] ; lock       ;
; N/A   ; None         ; 9.900 ns   ; DataOut0[0]~reg0 ; DataOut0[0] ; lock       ;
+-------+--------------+------------+------------------+-------------+------------+


+------------------------------------------------------------------------------------+
; th                                                                                 ;
+---------------+-------------+-----------+------------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From       ; To               ; To Clock ;
+---------------+-------------+-----------+------------+------------------+----------+
; N/A           ; None        ; 1.000 ns  ; DataIn0[2] ; DataOut0[2]~reg0 ; lock     ;
; N/A           ; None        ; 0.900 ns  ; DataIn1[0] ; DataOut1[0]~reg0 ; lock     ;
; N/A           ; None        ; 0.900 ns  ; DataIn0[3] ; DataOut0[3]~reg0 ; lock     ;
; N/A           ; None        ; 0.900 ns  ; DataIn0[1] ; DataOut0[1]~reg0 ; lock     ;
; N/A           ; None        ; 0.900 ns  ; DataIn0[0] ; DataOut0[0]~reg0 ; lock     ;
; N/A           ; None        ; -1.100 ns ; DataIn3[2] ; DataOut3[2]~reg0 ; lock     ;
; N/A           ; None        ; -1.100 ns ; DataIn2[3] ; DataOut2[3]~reg0 ; lock     ;
; N/A           ; None        ; -1.100 ns ; DataIn2[0] ; DataOut2[0]~reg0 ; lock     ;
; N/A           ; None        ; -1.200 ns ; DataIn3[3] ; DataOut3[3]~reg0 ; lock     ;
; N/A           ; None        ; -1.200 ns ; DataIn3[1] ; DataOut3[1]~reg0 ; lock     ;
; N/A           ; None        ; -1.200 ns ; DataIn3[0] ; DataOut3[0]~reg0 ; lock     ;
; N/A           ; None        ; -1.200 ns ; DataIn2[2] ; DataOut2[2]~reg0 ; lock     ;
; N/A           ; None        ; -1.200 ns ; DataIn2[1] ; DataOut2[1]~reg0 ; lock     ;
; N/A           ; None        ; -1.400 ns ; DataIn1[3] ; DataOut1[3]~reg0 ; lock     ;
; N/A           ; None        ; -1.400 ns ; DataIn1[2] ; DataOut1[2]~reg0 ; lock     ;
; N/A           ; None        ; -1.400 ns ; DataIn1[1] ; DataOut1[1]~reg0 ; lock     ;
+---------------+-------------+-----------+------------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sun Mar 09 21:08:13 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "lock" is an undefined clock
Info: No valid register-to-register data paths exist for clock "lock"
Info: tsu for register "DataOut1[3]~reg0" (data pin = "DataIn1[3]", clock pin = "lock") is 4.100 ns
    Info: + Longest pin to register delay is 6.700 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_69; Fanout = 1; PIN Node = 'DataIn1[3]'
        Info: 2: + IC(2.700 ns) + CELL(0.900 ns) = 6.700 ns; Loc. = LC1_A7; Fanout = 1; REG Node = 'DataOut1[3]~reg0'
        Info: Total cell delay = 4.000 ns ( 59.70 % )
        Info: Total interconnect delay = 2.700 ns ( 40.30 % )
    Info: + Micro setup delay of destination is 1.300 ns
    Info: - Shortest clock path from clock "lock" to destination register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'lock'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_A7; Fanout = 1; REG Node = 'DataOut1[3]~reg0'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: tco from clock "lock" to destination pin "DataOut3[3]" through register "DataOut3[3]~reg0" is 10.900 ns
    Info: + Longest clock path from clock "lock" to source register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'lock'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_A16; Fanout = 1; REG Node = 'DataOut3[3]~reg0'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Longest register to pin delay is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_A16; Fanout = 1; REG Node = 'DataOut3[3]~reg0'
        Info: 2: + IC(2.200 ns) + CELL(3.900 ns) = 6.100 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'DataOut3[3]'
        Info: Total cell delay = 3.900 ns ( 63.93 % )
        Info: Total interconnect delay = 2.200 ns ( 36.07 % )
Info: th for register "DataOut0[2]~reg0" (data pin = "DataIn0[2]", clock pin = "lock") is 1.000 ns
    Info: + Longest clock path from clock "lock" to destination register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'lock'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC7_C23; Fanout = 1; REG Node = 'DataOut0[2]~reg0'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro hold delay of destination is 1.400 ns
    Info: - Shortest pin to register delay is 4.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_44; Fanout = 1; PIN Node = 'DataIn0[2]'
        Info: 2: + IC(1.500 ns) + CELL(0.900 ns) = 4.300 ns; Loc. = LC7_C23; Fanout = 1; REG Node = 'DataOut0[2]~reg0'
        Info: Total cell delay = 2.800 ns ( 65.12 % )
        Info: Total interconnect delay = 1.500 ns ( 34.88 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Mar 09 21:08:14 2008
    Info: Elapsed time: 00:00:02