timing.vhd

一个用vhdl写的时钟代码

-------分钟与小时计时的模块(与外部联系可设置计时模式)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity timing is
port(clr_time : in std_logic;
	 setclk_h : in std_logic;
	 setclk_m : in std_logic;
	 select12_24 : in std_logic;--'0'==12   '1'==24
	 data_min_l : out std_logic_vector(3 downto 0);--分的低位
	 data_min_h : out std_logic_vector(3 downto 0);--分的高位
	 data_hou_l : out std_logic_vector(3 downto 0);--小时的低位
	 data_hou_h : out std_logic_vector(3 downto 0));--小时的高位
end entity;
---------------------------------------------------------
architecture behave of timing is
component count10 is---------------------------count10
port(clk1 : in std_logic;
		 clr1 : in std_logic;--------------'1'enable
		 carry1 : out std_logic;
		 value1 : out std_logic_vector(3 downto 0));
end component;
component count6 is ---------------------------count6
	port(clk2 : in std_logic;
		 clr2 : in std_logic;
		 carry2 : out std_logic;
		 value2 : out std_logic_vector(3 downto 0));
end component;
component count12 is----------------------------count12
port(clk3 : in std_logic;
		clr3 : in std_logic;
		value_l: out std_logic_vector(3 downto 0);
		value_h: out std_logic_vector(3 downto 0)
		);
end component;
component count24 is----------------------------count24
port(clk4 : in std_logic;
		clr4 : in std_logic;
		value_lb: out std_logic_vector(3 downto 0);
		value_hb: out std_logic_vector(3 downto 0)
		);
end component;
signal data_temp1,data_temp2 : std_logic_vector(3 downto 0);--12小时hour_l  ,  hour_h;
signal data_temp3,data_temp4 : std_logic_vector(3 downto 0);--24小时hour_l  ,  hour_h;
signal clk_temp1,clk_temp2 : std_logic;
signal carry_temp1,carry_temp2 : std_logic;
  begin
U1:  count10 port map(setclk_m,clr_time,carry_temp1,data_min_l);
U2:  count6 port map(carry_temp1,clr_time,carry_temp2,data_min_h);
U3:  count12 port map(carry_temp2 or setclk_h,clr_time,data_temp1,data_temp2);
U4:  count24 port map(carry_temp2 or setclk_h,clr_time,data_temp3,data_temp4);
--U5:  count12 port map(setclk_h,clr_time,data_temp1,data_temp2);
--U6:  count24 port map(setclk_h,clr_time,data_temp3,data_temp4);
 process(setclk_h,setclk_m,select12_24)
 begin
 --if con_key = "01" then
 	if select12_24 = '0' then data_hou_l <= data_temp1;
							  data_hou_h <= data_temp2;
    else data_hou_l <= data_temp3;
	     data_hou_h <= data_temp4;
 	end if;
 --end if;
end process;
end architecture;