count12.vhd

一个用vhdl写的时钟代码

---------12进制计数作为一个整体
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count12 is
	port(clk3 : in std_logic;
		clr3 : in std_logic;
		value_l: out std_logic_vector(3 downto 0);
		value_h: out std_logic_vector(3 downto 0)
		);
end entity count12;
------------------------------------------
architecture behave of count12 is
 signal temp : std_logic_vector(3 downto 0);
  begin
P1: process(clk3,clr3)
	begin
	if clr3='1' then temp <=(others =>'0');
	elsif clk3'event and clk3='1' then
		if temp <11 then temp <= temp + 1;
		else temp <=(others =>'0');
		end if;
	else null;
	end if;
 end process;
P2: process(clk3,temp,clr3)
	 begin
	case temp is
	when "0000" => value_l <= (others =>'0');-------------00
					value_h <= (others =>'0');
	when "0001" => value_l <= "0001";---------------------01
				    value_h <="0000";
	when "0010" => value_l <= "0010";---------------------02
					value_h <="0000" ;
	when "0011" => value_l <= "0011";---------------------03
					value_h <="0000" ;
	when "0100" => value_l <= "0100";---------------------04
					value_h <="0000";
	when "0101" => value_l <= "0101";---------------------05
					value_h <="0000" ;
	when "0110" => value_l <= "0110";---------------------06
					value_h <= "0000";
	when "0111" => value_l <= "0111";---------------------07
					value_h <= "0000";
	when "1000" => value_l <= "1000";---------------------08
					value_h <="0000" ;
	when "1001" => value_l <= "1001";---------------------09
					value_h <= "0000";
	when "1010" => value_l <= "0000";---------------------10
					value_h <= "0001";
	when "1011" => value_l <= "0001";---------------------11
					value_h <= "0001";
	when others => null;
   end case;
end process;
end architecture behave;