zz.map.qmsg

基于FPGA的交通灯系统控制程序。用的是verilog.

{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bleft\[5\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bleft\[5\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bleft\[4\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bleft\[4\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bleft\[3\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bleft\[3\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bleft\[2\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bleft\[2\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bleft\[1\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bleft\[1\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bleft\[0\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bleft\[0\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "bgreen traffic.v(11) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable \"bgreen\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 11 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bgreen\[7\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bgreen\[7\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bgreen\[6\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bgreen\[6\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bgreen\[5\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bgreen\[5\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bgreen\[4\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bgreen\[4\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bgreen\[3\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bgreen\[3\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bgreen\[2\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bgreen\[2\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bgreen\[1\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bgreen\[1\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bgreen\[0\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bgreen\[0\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(46) " "Warning (10230): Verilog HDL assignment warning at traffic.v(46): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 46 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(48) " "Warning (10230): Verilog HDL assignment warning at traffic.v(48): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 48 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(79) " "Warning (10230): Verilog HDL assignment warning at traffic.v(79): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 79 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 traffic.v(81) " "Warning (10230): Verilog HDL assignment warning at traffic.v(81): truncated value with size 32 to match size of target (4)" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 81 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "traffic:inst\|numa\[7\] " "Warning: No clock transition on \"traffic:inst\|numa\[7\]\" register due to stuck clock or clock enable" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 56 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "traffic:inst\|numa\[7\] clock_enable GND " "Warning: Reduced register \"traffic:inst\|numa\[7\]\" with stuck clock_enable port to stuck value GND" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 56 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "traffic:inst\|numa\[6\] " "Warning: No clock transition on \"traffic:inst\|numa\[6\]\" register due to stuck clock or clock enable" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 56 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "traffic:inst\|numa\[6\] clock_enable GND " "Warning: Reduced register \"traffic:inst\|numa\[6\]\" with stuck clock_enable port to stuck value GND" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 56 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "traffic:inst\|numa\[5\] " "Warning: No clock transition on \"traffic:inst\|numa\[5\]\" register due to stuck clock or clock enable" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 56 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "traffic:inst\|numa\[5\] clock_enable GND " "Warning: Reduced register \"traffic:inst\|numa\[5\]\" with stuck clock_enable port to stuck value GND" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 56 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "traffic:inst\|numa\[4\] " "Warning: No clock transition on \"traffic:inst\|numa\[4\]\" register due to stuck clock or clock enable" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 56 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "traffic:inst\|numa\[4\] clock_enable GND " "Warning: Reduced register \"traffic:inst\|numa\[4\]\" with stuck clock_enable port to stuck value GND" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 56 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "traffic:inst\|numa\[3\] " "Warning: No clock transition on \"traffic:inst\|numa\[3\]\" register due to stuck clock or clock enable" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 56 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "traffic:inst\|numa\[3\] clock_enable GND " "Warning: Reduced register \"traffic:inst\|numa\[3\]\" with stuck clock_enable port to stuck value GND" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 56 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "traffic:inst\|numa\[2\] " "Warning: No clock transition on \"traffic:inst\|numa\[2\]\" register due to stuck clock or clock enable" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 56 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "traffic:inst\|numa\[2\] clock_enable GND " "Warning: Reduced register \"traffic:inst\|numa\[2\]\" with stuck clock_enable port to stuck value GND" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 56 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "traffic:inst\|numa\[1\] " "Warning: No clock transition on \"traffic:inst\|numa\[1\]\" register due to stuck clock or clock enable" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 56 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "traffic:inst\|numa\[1\] clock_enable GND " "Warning: Reduced register \"traffic:inst\|numa\[1\]\" with stuck clock_enable port to stuck value GND" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 56 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "traffic:inst\|numa\[0\] " "Warning: No clock transition on \"traffic:inst\|numa\[0\]\" register due to stuck clock or clock enable" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 56 -1 0 } }  } 0 0 "No clock transition on \"%1!s!\" register due to stuck clock or clock enable" 0 0}