zz.map.qmsg

基于FPGA的交通灯系统控制程序。用的是verilog.

{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "agreen\[3\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"agreen\[3\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "agreen\[2\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"agreen\[2\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "agreen\[1\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"agreen\[1\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "agreen\[0\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"agreen\[0\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "aleft traffic.v(11) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable \"aleft\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 11 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "aleft\[7\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"aleft\[7\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "aleft\[6\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"aleft\[6\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "aleft\[5\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"aleft\[5\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "aleft\[4\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"aleft\[4\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "aleft\[3\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"aleft\[3\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "aleft\[2\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"aleft\[2\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "aleft\[1\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"aleft\[1\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "aleft\[0\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"aleft\[0\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "bred traffic.v(11) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable \"bred\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 11 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bred\[7\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bred\[7\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bred\[6\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bred\[6\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bred\[5\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bred\[5\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bred\[4\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bred\[4\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bred\[3\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bred\[3\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bred\[2\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bred\[2\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bred\[1\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bred\[1\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bred\[0\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bred\[0\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "byellow traffic.v(11) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable \"byellow\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 11 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "byellow\[7\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"byellow\[7\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "byellow\[6\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"byellow\[6\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "byellow\[5\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"byellow\[5\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "byellow\[4\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"byellow\[4\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "byellow\[3\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"byellow\[3\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "byellow\[2\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"byellow\[2\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "byellow\[1\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"byellow\[1\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "byellow\[0\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"byellow\[0\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "bleft traffic.v(11) " "Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable \"bleft\", which holds its previous value in one or more paths through the always construct" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 11 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bleft\[7\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bleft\[7\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "bleft\[6\] traffic.v(8) " "Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for \"bleft\[6\]\"" {  } { { "traffic.v" "" { Text "D:/traffic light/traffic.v" 8 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}