zz.map.rpt

基于FPGA的交通灯系统控制程序。用的是verilog.

Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "aleft[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "aleft[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "aleft[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "aleft[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "aleft[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "aleft[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "aleft[0]"
Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable "bred", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bred[7]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bred[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bred[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bred[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bred[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bred[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bred[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bred[0]"
Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable "byellow", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "byellow[7]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "byellow[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "byellow[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "byellow[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "byellow[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "byellow[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "byellow[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "byellow[0]"
Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable "bleft", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bleft[7]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bleft[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bleft[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bleft[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bleft[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bleft[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bleft[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bleft[0]"
Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable "bgreen", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bgreen[7]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bgreen[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bgreen[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bgreen[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bgreen[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bgreen[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bgreen[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "bgreen[0]"
Warning (10230): Verilog HDL assignment warning at traffic.v(46): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at traffic.v(48): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at traffic.v(79): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at traffic.v(81): truncated value with size 32 to match size of target (4)
Warning: No clock transition on "traffic:inst|numa[7]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numa[7]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "traffic:inst|numa[6]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numa[6]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "traffic:inst|numa[5]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numa[5]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "traffic:inst|numa[4]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numa[4]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "traffic:inst|numa[3]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numa[3]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "traffic:inst|numa[2]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numa[2]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "traffic:inst|numa[1]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numa[1]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "traffic:inst|numa[0]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numa[0]" with stuck clock_enable port to stuck value GND
Info: Power-up level of register "traffic:inst|LAMPA[3]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "traffic:inst|LAMPA[3]" with stuck data_in port to stuck value VCC
Warning: Reduced register "traffic:inst|LAMPA[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "traffic:inst|LAMPA[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "traffic:inst|LAMPA[0]" with stuck data_in port to stuck value GND
Warning: No clock transition on "traffic:inst|numb[7]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numb[7]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "traffic:inst|numb[6]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numb[6]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "traffic:inst|numb[5]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numb[5]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "traffic:inst|numb[4]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numb[4]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "traffic:inst|numb[3]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numb[3]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "traffic:inst|numb[2]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numb[2]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "traffic:inst|numb[1]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numb[1]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "traffic:inst|numb[0]" register due to stuck clock or clock enable
Warning: Reduced register "traffic:inst|numb[0]" with stuck clock_enable port to stuck value GND
Info: State machine "|zz|traffic:inst|counta" contains 5 states
Info: State machine "|zz|traffic:inst|countb" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|zz|traffic:inst|counta"
Info: Encoding result for state machine "|zz|traffic:inst|counta"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "traffic:inst|counta.001"
        Info: Encoded state bit "traffic:inst|counta.010"
        Info: Encoded state bit "traffic:inst|counta.011"
        Info: Encoded state bit "traffic:inst|counta.000"
        Info: Encoded state bit "traffic:inst|counta.100"
    Info: State "|zz|traffic:inst|counta.000" uses code string "00000"
    Info: State "|zz|traffic:inst|counta.011" uses code string "00110"
    Info: State "|zz|traffic:inst|counta.010" uses code string "01010"
    Info: State "|zz|traffic:inst|counta.100" uses code string "00011"
    Info: State "|zz|traffic:inst|counta.001" uses code string "10010"
Info: Selected Auto state machine encoding method for state machine "|zz|traffic:inst|countb"
Info: Encoding result for state machine "|zz|traffic:inst|countb"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "traffic:inst|countb.001"
        Info: Encoded state bit "traffic:inst|countb.010"
        Info: Encoded state bit "traffic:inst|countb.011"
        Info: Encoded state bit "traffic:inst|countb.000"
        Info: Encoded state bit "traffic:inst|countb.100"
    Info: State "|zz|traffic:inst|countb.000" uses code string "00000"
    Info: State "|zz|traffic:inst|countb.011" uses code string "00110"
    Info: State "|zz|traffic:inst|countb.010" uses code string "01010"
    Info: State "|zz|traffic:inst|countb.100" uses code string "00011"
    Info: State "|zz|traffic:inst|countb.001" uses code string "10010"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "out[3]" stuck at VCC
    Warning: Pin "out[2]" stuck at GND
    Warning: Pin "out[1]" stuck at GND
    Warning: Pin "out[0]" stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "clk"
Info: Implemented 5 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 4 output pins
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 57 warnings
    Info: Processing ended: Sat Sep 22 16:56:27 2001
    Info: Elapsed time: 00:00:02