zz.map.rpt

基于FPGA的交通灯系统控制程序。用的是verilog.

; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 0     ;
;     -- Combinational with no register       ; 0     ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 0     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 0     ;
;     -- 2 input functions                    ; 0     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 0     ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 0     ;
; I/O pins                                    ; 5     ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |zz                        ; 0 (0)       ; 0            ; 0           ; 0    ; 5    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |zz                 ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------+
; State Machine - |zz|traffic:inst|counta                                     ;
+------------+------------+------------+------------+------------+------------+
; Name       ; counta.001 ; counta.010 ; counta.011 ; counta.000 ; counta.100 ;
+------------+------------+------------+------------+------------+------------+
; counta.000 ; 0          ; 0          ; 0          ; 0          ; 0          ;
; counta.011 ; 0          ; 0          ; 1          ; 1          ; 0          ;
; counta.010 ; 0          ; 1          ; 0          ; 1          ; 0          ;
; counta.100 ; 0          ; 0          ; 0          ; 1          ; 1          ;
; counta.001 ; 1          ; 0          ; 0          ; 1          ; 0          ;
+------------+------------+------------+------------+------------+------------+


+-----------------------------------------------------------------------------+
; State Machine - |zz|traffic:inst|countb                                     ;
+------------+------------+------------+------------+------------+------------+
; Name       ; countb.001 ; countb.010 ; countb.011 ; countb.000 ; countb.100 ;
+------------+------------+------------+------------+------------+------------+
; countb.000 ; 0          ; 0          ; 0          ; 0          ; 0          ;
; countb.011 ; 0          ; 0          ; 1          ; 1          ; 0          ;
; countb.010 ; 0          ; 1          ; 0          ; 1          ; 0          ;
; countb.100 ; 0          ; 0          ; 0          ; 1          ; 1          ;
; countb.001 ; 1          ; 0          ; 0          ; 1          ; 0          ;
+------------+------------+------------+------------+------------+------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Sep 22 16:56:26 2001
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off zz -c zz
Warning (10226): Verilog HDL Multiple Declaration warning at traffic.v(9): net, port, or variable "LAMPA" was previously declared without a range
Info (10151): Verilog HDL Declaration information at traffic.v(3): "LAMPA" is declared here
Warning (10226): Verilog HDL Multiple Declaration warning at traffic.v(9): net, port, or variable "LAMPB" was previously declared without a range
Info (10151): Verilog HDL Declaration information at traffic.v(3): "LAMPB" is declared here
Info: Found 1 design units, including 1 entities, in source file traffic.v
    Info: Found entity 1: traffic
Info: Found 1 design units, including 1 entities, in source file zz.bdf
    Info: Found entity 1: zz
Info: Elaborating entity "zz" for the top level hierarchy
Info: Elaborating entity "traffic" for hierarchy "traffic:inst"
Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable "ared", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ared[7]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ared[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ared[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ared[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ared[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ared[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ared[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ared[0]"
Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable "ayellow", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ayellow[7]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ayellow[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ayellow[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ayellow[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ayellow[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ayellow[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ayellow[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "ayellow[0]"
Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable "agreen", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "agreen[7]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "agreen[6]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "agreen[5]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "agreen[4]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "agreen[3]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "agreen[2]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "agreen[1]"
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "agreen[0]"
Warning (10240): Verilog HDL Always Construct warning at traffic.v(11): inferring latch(es) for variable "aleft", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at traffic.v(8): inferred latch for "aleft[7]"