shift_clk.csf.msg

vhdl编写的一个完整工程

{  Info "ITAN_SLACK_ANALYSIS" "" "Found complex timing assignments. Calculating slack delays instead of fmax." {  } {  }  }
{  Info "ITDB_FULL_SLACK_RESULT" "6.55 ns shift_pll:inst\|altpll:altpll_component\|_clk0 register inst2 register inst2 " "Slack time is 6.55 ns for clock shift_pll:inst\|altpll:altpll_component\|_clk0 between source register inst2 and destination register inst2" { { Info "ITDB_FULL_P2P_REQUIREMENT_RESULT" "+ Largest register register 7.287 ns " "+ Largest register to register requirement is 7.287 ns" { { Info "ITDB_FULL_SETUP_REQUIREMENT" "+ 7.500 ns " "+ Setup relationship between source and destination is 7.500 ns" { { Info "ITDB_EDGE_RESULT" "+ Latch 6.063 ns " "+ Latch edge is 6.063 ns" { { Info "ITDB_CLOCK_SETTING_RESULT" "Destination shift_pll:inst\|altpll:altpll_component\|_clk0 7.500 ns  -1.437 ns " "Clock period of Destination clock shift_pll:inst\|altpll:altpll_component\|_clk0 is 7.500 ns with  offset of -1.437 ns" {  } {  } } { Info "ITDB_MULTICYCLE_RESULT" "Setup Destination 1 " "Multicycle Setup factor for Destination register is 1" {  } {  } }  } {  } } { Info "ITDB_EDGE_RESULT" "- Launch -1.437 ns " "- Launch edge is -1.437 ns" { { Info "ITDB_CLOCK_SETTING_RESULT" "Source shift_pll:inst\|altpll:altpll_component\|_clk0 7.500 ns  -1.437 ns " "Clock period of Source clock shift_pll:inst\|altpll:altpll_component\|_clk0 is 7.500 ns with  offset of -1.437 ns" {  } {  } } { Info "ITDB_MULTICYCLE_RESULT" "Setup Source 1 " "Multicycle Setup factor for Source register is 1" {  } {  } }  } {  } }  } {  } } { Info "ITDB_FULL_CLOCK_SKEW_RESULT" "+ Largest 0.000 ns " "+ Largest clock skew is 0.000 ns" { { Info "ITDB_FULL_CLOCK_PATH_RESULT" "+ Shortest shift_pll:inst\|altpll:altpll_component\|_clk0 destination register 2.335 ns " "+ Shortest clock path from clock shift_pll:inst\|altpll:altpll_component\|_clk0 to destination register is 2.335 ns" { { Info "ITDB_NODE_DELAY" "1 IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL_X27_Y31_N0 CLK shift_pll:inst\|altpll:altpll_component\|_clk0 " "1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_X27_Y31_N0; CLK Node = 'shift_pll:inst\|altpll:altpll_component\|_clk0'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "" { shift_pll:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } } { "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" "" "" { Text "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" 472 3 0 } }  } } { Info "ITDB_NODE_DELAY" "2 IC(1.691 ns) + CELL(0.644 ns) 2.335 ns LC_X1_Y9_N2 REG inst2 " "2: + IC(1.691 ns) + CELL(0.644 ns) = 2.335 ns; Loc. = LC_X1_Y9_N2; REG Node = 'inst2'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk0 inst2 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 296 424 488 376 "inst2" "" } } } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk0 inst2 } "NODE_NAME" } } }  } } { Info "ITDB_FULL_CLOCK_PATH_RESULT" "- Longest shift_pll:inst\|altpll:altpll_component\|_clk0 source register 2.335 ns " "- Longest clock path from clock shift_pll:inst\|altpll:altpll_component\|_clk0 to source register is 2.335 ns" { { Info "ITDB_NODE_DELAY" "1 IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL_X27_Y31_N0 CLK shift_pll:inst\|altpll:altpll_component\|_clk0 " "1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_X27_Y31_N0; CLK Node = 'shift_pll:inst\|altpll:altpll_component\|_clk0'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "" { shift_pll:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } } } { "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" "" "" { Text "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" 472 3 0 } }  } } { Info "ITDB_NODE_DELAY" "2 IC(1.691 ns) + CELL(0.644 ns) 2.335 ns LC_X1_Y9_N2 REG inst2 " "2: + IC(1.691 ns) + CELL(0.644 ns) = 2.335 ns; Loc. = LC_X1_Y9_N2; REG Node = 'inst2'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk0 inst2 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 296 424 488 376 "inst2" "" } } } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk0 inst2 } "NODE_NAME" } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk0 inst2 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk0 inst2 } "NODE_NAME" } } }  } } { Info "ITDB_FULL_TCO_DELAY" "- 0.202 ns " "- Micro clock to output delay of source is 0.202 ns" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 296 424 488 376 "inst2" "" } } } } }  } } { Info "ITDB_FULL_TSU_DELAY" "- 0.011 ns " "- Micro setup delay of destination is 0.011 ns" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 296 424 488 376 "inst2" "" } } } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk0 inst2 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk0 inst2 } "NODE_NAME" } } }  } } { Info "ITDB_FULL_DATA_PATH_RESULT" "- Longest register register 0.737 ns " "- Longest register to register delay is 0.737 ns" { { Info "ITDB_NODE_DELAY" "1 IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LC_X1_Y9_N2 REG inst2 " "1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y9_N2; REG Node = 'inst2'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "" { inst2 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 296 424 488 376 "inst2" "" } } } } }  } } { Info "ITDB_NODE_DELAY" "2 IC(0.467 ns) + CELL(0.270 ns) 0.737 ns LC_X1_Y9_N2 REG inst2 " "2: + IC(0.467 ns) + CELL(0.270 ns) = 0.737 ns; Loc. = LC_X1_Y9_N2; REG Node = 'inst2'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "0.737 ns" { inst2 inst2 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 296 424 488 376 "inst2" "" } } } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "0.737 ns" { inst2 inst2 } "NODE_NAME" } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk0 inst2 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk0 inst2 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "0.737 ns" { inst2 inst2 } "NODE_NAME" } } }  }  }
{  Info "ITDB_FULL_SLACK_RESULT" "4.05 ns shift_pll:inst\|altpll:altpll_component\|_clk1 register inst4 register inst4 " "Slack time is 4.05 ns for clock shift_pll:inst\|altpll:altpll_component\|_clk1 between source register inst4 and destination register inst4" { { Info "ITDB_FULL_P2P_REQUIREMENT_RESULT" "+ Largest register register 4.787 ns " "+ Largest register to register requirement is 4.787 ns" { { Info "ITDB_FULL_SETUP_REQUIREMENT" "+ 5.000 ns " "+ Setup relationship between source and destination is 5.000 ns" { { Info "ITDB_EDGE_RESULT" "+ Latch 3.563 ns " "+ Latch edge is 3.563 ns" { { Info "ITDB_CLOCK_SETTING_RESULT" "Destination shift_pll:inst\|altpll:altpll_component\|_clk1 5.000 ns  -1.437 ns " "Clock period of Destination clock shift_pll:inst\|altpll:altpll_component\|_clk1 is 5.000 ns with  offset of -1.437 ns" {  } {  } } { Info "ITDB_MULTICYCLE_RESULT" "Setup Destination 1 " "Multicycle Setup factor for Destination register is 1" {  } {  } }  } {  } } { Info "ITDB_EDGE_RESULT" "- Launch -1.437 ns " "- Launch edge is -1.437 ns" { { Info "ITDB_CLOCK_SETTING_RESULT" "Source shift_pll:inst\|altpll:altpll_component\|_clk1 5.000 ns  -1.437 ns " "Clock period of Source clock shift_pll:inst\|altpll:altpll_component\|_clk1 is 5.000 ns with  offset of -1.437 ns" {  } {  } } { Info "ITDB_MULTICYCLE_RESULT" "Setup Source 1 " "Multicycle Setup factor for Source register is 1" {  } {  } }  } {  } }  } {  } } { Info "ITDB_FULL_CLOCK_SKEW_RESULT" "+ Largest 0.000 ns " "+ Largest clock skew is 0.000 ns" { { Info "ITDB_FULL_CLOCK_PATH_RESULT" "+ Shortest shift_pll:inst\|altpll:altpll_component\|_clk1 destination register 2.335 ns " "+ Shortest clock path from clock shift_pll:inst\|altpll:altpll_component\|_clk1 to destination register is 2.335 ns" { { Info "ITDB_NODE_DELAY" "1 IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL_X27_Y31_N0 CLK shift_pll:inst\|altpll:altpll_component\|_clk1 " "1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_X27_Y31_N0; CLK Node = 'shift_pll:inst\|altpll:altpll_component\|_clk1'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "" { shift_pll:inst|altpll:altpll_component|_clk1 } "NODE_NAME" } } } { "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" "" "" { Text "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" 469 3 0 } }  } } { Info "ITDB_NODE_DELAY" "2 IC(1.691 ns) + CELL(0.644 ns) 2.335 ns LC_X1_Y4_N2 REG inst4 " "2: + IC(1.691 ns) + CELL(0.644 ns) = 2.335 ns; Loc. = LC_X1_Y4_N2; REG Node = 'inst4'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk1 inst4 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 384 424 488 464 "inst4" "" } } } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk1 inst4 } "NODE_NAME" } } }  } } { Info "ITDB_FULL_CLOCK_PATH_RESULT" "- Longest shift_pll:inst\|altpll:altpll_component\|_clk1 source register 2.335 ns " "- Longest clock path from clock shift_pll:inst\|altpll:altpll_component\|_clk1 to source register is 2.335 ns" { { Info "ITDB_NODE_DELAY" "1 IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL_X27_Y31_N0 CLK shift_pll:inst\|altpll:altpll_component\|_clk1 " "1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_X27_Y31_N0; CLK Node = 'shift_pll:inst\|altpll:altpll_component\|_clk1'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "" { shift_pll:inst|altpll:altpll_component|_clk1 } "NODE_NAME" } } } { "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" "" "" { Text "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" 469 3 0 } }  } } { Info "ITDB_NODE_DELAY" "2 IC(1.691 ns) + CELL(0.644 ns) 2.335 ns LC_X1_Y4_N2 REG inst4 " "2: + IC(1.691 ns) + CELL(0.644 ns) = 2.335 ns; Loc. = LC_X1_Y4_N2; REG Node = 'inst4'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk1 inst4 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 384 424 488 464 "inst4" "" } } } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk1 inst4 } "NODE_NAME" } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk1 inst4 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk1 inst4 } "NODE_NAME" } } }  } } { Info "ITDB_FULL_TCO_DELAY" "- 0.202 ns " "- Micro clock to output delay of source is 0.202 ns" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 384 424 488 464 "inst4" "" } } } } }  } } { Info "ITDB_FULL_TSU_DELAY" "- 0.011 ns " "- Micro setup delay of destination is 0.011 ns" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 384 424 488 464 "inst4" "" } } } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk1 inst4 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk1 inst4 } "NODE_NAME" } } }  } } { Info "ITDB_FULL_DATA_PATH_RESULT" "- Longest register register 0.737 ns " "- Longest register to register delay is 0.737 ns" { { Info "ITDB_NODE_DELAY" "1 IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LC_X1_Y4_N2 REG inst4 " "1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N2; REG Node = 'inst4'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "" { inst4 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 384 424 488 464 "inst4" "" } } } } }  } } { Info "ITDB_NODE_DELAY" "2 IC(0.467 ns) + CELL(0.270 ns) 0.737 ns LC_X1_Y4_N2 REG inst4 " "2: + IC(0.467 ns) + CELL(0.270 ns) = 0.737 ns; Loc. = LC_X1_Y4_N2; REG Node = 'inst4'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "0.737 ns" { inst4 inst4 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 384 424 488 464 "inst4" "" } } } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "0.737 ns" { inst4 inst4 } "NODE_NAME" } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk1 inst4 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk1 inst4 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "0.737 ns" { inst4 inst4 } "NODE_NAME" } } }  }  }
{  Info "ITDB_FULL_SLACK_RESULT" "4.05 ns shift_pll:inst\|altpll:altpll_component\|_clk2 register inst5 register inst5 " "Slack time is 4.05 ns for clock shift_pll:inst\|altpll:altpll_component\|_clk2 between source register inst5 and destination register inst5" { { Info "ITDB_FULL_P2P_REQUIREMENT_RESULT" "+ Largest register register 4.787 ns " "+ Largest register to register requirement is 4.787 ns" { { Info "ITDB_FULL_SETUP_REQUIREMENT" "+ 5.000 ns " "+ Setup relationship between source and destination is 5.000 ns" { { Info "ITDB_EDGE_RESULT" "+ Latch 4.563 ns " "+ Latch edge is 4.563 ns" { { Info "ITDB_CLOCK_SETTING_RESULT" "Destination shift_pll:inst\|altpll:altpll_component\|_clk2 5.000 ns  -0.437 ns " "Clock period of Destination clock shift_pll:inst\|altpll:altpll_component\|_clk2 is 5.000 ns with  offset of -0.437 ns" {  } {  } } { Info "ITDB_MULTICYCLE_RESULT" "Setup Destination 1 " "Multicycle Setup factor for Destination register is 1" {  } {  } }  } {  } } { Info "ITDB_EDGE_RESULT" "- Launch -0.437 ns " "- Launch edge is -0.437 ns" { { Info "ITDB_CLOCK_SETTING_RESULT" "Source shift_pll:inst\|altpll:altpll_component\|_clk2 5.000 ns  -0.437 ns " "Clock period of Source clock shift_pll:inst\|altpll:altpll_component\|_clk2 is 5.000 ns with  offset of -0.437 ns" {  } {  } } { Info "ITDB_MULTICYCLE_RESULT" "Setup Source 1 " "Multicycle Setup factor for Source register is 1" {  } {  } }  } {  } }  } {  } } { Info "ITDB_FULL_CLOCK_SKEW_RESULT" "+ Largest 0.000 ns " "+ Largest clock skew is 0.000 ns" { { Info "ITDB_FULL_CLOCK_PATH_RESULT" "+ Shortest shift_pll:inst\|altpll:altpll_component\|_clk2 destination register 2.335 ns " "+ Shortest clock path from clock shift_pll:inst\|altpll:altpll_component\|_clk2 to destination register is 2.335 ns" { { Info "ITDB_NODE_DELAY" "1 IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL_X27_Y31_N0 CLK shift_pll:inst\|altpll:altpll_component\|_clk2 " "1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_X27_Y31_N0; CLK Node = 'shift_pll:inst\|altpll:altpll_component\|_clk2'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "" { shift_pll:inst|altpll:altpll_component|_clk2 } "NODE_NAME" } } } { "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" "" "" { Text "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" 466 3 0 } }  } } { Info "ITDB_NODE_DELAY" "2 IC(1.691 ns) + CELL(0.644 ns) 2.335 ns LC_X17_Y30_N2 REG inst5 " "2: + IC(1.691 ns) + CELL(0.644 ns) = 2.335 ns; Loc. = LC_X17_Y30_N2; REG Node = 'inst5'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk2 inst5 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 472 424 488 552 "inst5" "" } } } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk2 inst5 } "NODE_NAME" } } }  } } { Info "ITDB_FULL_CLOCK_PATH_RESULT" "- Longest shift_pll:inst\|altpll:altpll_component\|_clk2 source register 2.335 ns " "- Longest clock path from clock shift_pll:inst\|altpll:altpll_component\|_clk2 to source register is 2.335 ns" { { Info "ITDB_NODE_DELAY" "1 IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL_X27_Y31_N0 CLK shift_pll:inst\|altpll:altpll_component\|_clk2 " "1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_X27_Y31_N0; CLK Node = 'shift_pll:inst\|altpll:altpll_component\|_clk2'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "" { shift_pll:inst|altpll:altpll_component|_clk2 } "NODE_NAME" } } } { "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" "" "" { Text "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" 466 3 0 } }  } } { Info "ITDB_NODE_DELAY" "2 IC(1.691 ns) + CELL(0.644 ns) 2.335 ns LC_X17_Y30_N2 REG inst5 " "2: + IC(1.691 ns) + CELL(0.644 ns) = 2.335 ns; Loc. = LC_X17_Y30_N2; REG Node = 'inst5'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk2 inst5 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 472 424 488 552 "inst5" "" } } } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk2 inst5 } "NODE_NAME" } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk2 inst5 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk2 inst5 } "NODE_NAME" } } }  } } { Info "ITDB_FULL_TCO_DELAY" "- 0.202 ns " "- Micro clock to output delay of source is 0.202 ns" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 472 424 488 552 "inst5" "" } } } } }  } } { Info "ITDB_FULL_TSU_DELAY" "- 0.011 ns " "- Micro setup delay of destination is 0.011 ns" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 472 424 488 552 "inst5" "" } } } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk2 inst5 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk2 inst5 } "NODE_NAME" } } }  } } { Info "ITDB_FULL_DATA_PATH_RESULT" "- Longest register register 0.737 ns " "- Longest register to register delay is 0.737 ns" { { Info "ITDB_NODE_DELAY" "1 IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LC_X17_Y30_N2 REG inst5 " "1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y30_N2; REG Node = 'inst5'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "" { inst5 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 472 424 488 552 "inst5" "" } } } } }  } } { Info "ITDB_NODE_DELAY" "2 IC(0.467 ns) + CELL(0.270 ns) 0.737 ns LC_X17_Y30_N2 REG inst5 " "2: + IC(0.467 ns) + CELL(0.270 ns) = 0.737 ns; Loc. = LC_X17_Y30_N2; REG Node = 'inst5'" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "0.737 ns" { inst5 inst5 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\shift_clk.bdf" { { { 472 424 488 552 "inst5" "" } } } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "0.737 ns" { inst5 inst5 } "NODE_NAME" } } }  } }  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk2 inst5 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "2.335 ns" { shift_pll:inst|altpll:altpll_component|_clk2 inst5 } "NODE_NAME" } } } { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" "" "" { Report "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk_everyone_V1_cmp.qrpt" Compiler "shift_clk" "everyone" "V1" "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\shift_clk\\db\\shift_clk.quartus_db" { Floorplan "" "" "0.737 ns" { inst5 inst5 } "NODE_NAME" } } }  }  }
{  Info "ITAN_REQUIREMENTS_MET" "" "All timing requirements were met. See Report window for more details." {  } {  }  }