shift_clk.csf.msg

vhdl编写的一个完整工程

{  Info "IMPP_MPP_USER_DEVICE" "EP1S10F780C7 shift_clk " "Selected device EP1S10F780C7 for design shift_clk" {  } {  }  }
{  Info "ICUT_CUT_YGR_PLL_DETERMINED_TYPE" "Enhanced shift_pll:inst\|altpll:altpll_component\|_clk0 " "Chose type Enhanced for Auto type PLL shift_pll:inst\|altpll:altpll_component\|_clk0" {  } {  }  }
{  Info "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO" "shift_pll:inst\|altpll:altpll_component\|_clk0 " "Can implement multiplication and division for ClockLock PLL shift_pll:inst\|altpll:altpll_component\|_clk0" { { Info "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "4 3 0 0 shift_pll:inst\|altpll:altpll_component\|_clk0 " "Implementing clock multiplication of 4, clock division of 3, and phase shift of 0 degrees (0 ps) for shift_pll:inst\|altpll:altpll_component\|_clk0 port" {  } {  } } { Info "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "2 1 0 0 shift_pll:inst\|altpll:altpll_component\|_clk1 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for shift_pll:inst\|altpll:altpll_component\|_clk1 port" {  } {  } } { Info "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "2 1 0 0 shift_pll:inst\|altpll:altpll_component\|_clk2 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for shift_pll:inst\|altpll:altpll_component\|_clk2 port" {  } {  } }  } {  }  }
{  Info "IMPP_MPP_ADVANCE_INFO" "EP1S10F780C7 " "Compilation Report contains advance information. Specifications for device EP1S10F780C7 are subject to change. Contact Altera for information on availability. No programming file will be generated." {  } {  }  }
{  Warning "WDAT_PRELIMINARY_TIMING" "EP1S10F780C7 " "Timing characteristics of device EP1S10F780C7 are preliminary" {  } {  }  }