shift_clk.csf.rpt

vhdl编写的一个完整工程

|AD26 |NC           |
|AD25 |NC           |
|AC3  |NC           |
|AD3  |NC           |
|AC4  |NC           |
|AD4  |NC           |
|E3   |NC           |
|E4   |NC           |
|D3   |NC           |
|D4   |NC           |
|P19  |NC           |
|AE26 |NC           |
|AH18 |NC           |
|AD7  |NC           |
|R10  |NC           |
|E5   |NC           |
|E11  |NC           |
|E22  |NC           |
+-----+-------------+------------+

+-----------------------------------------------------------------------------+
|Control Signals                                                              |
+-----------------------------------------------------------------------------+
+--------------------------------------------+--------------+-------+-----+------+--------------------+
|Name                                        |Location      |Fan-Out|Usage|Global|Global Resource Used|
+--------------------------------------------+--------------+-------+-----+------+--------------------+
|inclk0                                      |K17           |1      |Clock|no    |--                  |
|shift_pll:inst|altpll:altpll_component|_clk0|PLL_X27_Y31_N0|1      |Clock|yes   |Global clock        |
|shift_pll:inst|altpll:altpll_component|_clk1|PLL_X27_Y31_N0|1      |Clock|yes   |Global clock        |
|shift_pll:inst|altpll:altpll_component|_clk2|PLL_X27_Y31_N0|1      |Clock|yes   |Global clock        |
+--------------------------------------------+--------------+-------+-----+------+--------------------+

+-----------------------------------------------------------------------------+
|Global & Other Fast Signals                                                  |
+-----------------------------------------------------------------------------+
+--------------------------------------------+--------------+-------+--------------------+
|Name                                        |Location      |Fan-Out|Global Resource Used|
+--------------------------------------------+--------------+-------+--------------------+
|shift_pll:inst|altpll:altpll_component|_clk0|PLL_X27_Y31_N0|1      |Global clock        |
|shift_pll:inst|altpll:altpll_component|_clk1|PLL_X27_Y31_N0|1      |Global clock        |
|shift_pll:inst|altpll:altpll_component|_clk2|PLL_X27_Y31_N0|1      |Global clock        |
+--------------------------------------------+--------------+-------+--------------------+

+-----------------------------------------------------------------------------+
|Non-Global High Fan-Out Signals                                              |
+-----------------------------------------------------------------------------+
+------------------------------------------+-------+
|Name                                      |Fan-Out|
+------------------------------------------+-------+
|inst5                                     |2      |
|inst4                                     |2      |
|inst2                                     |2      |
|inclk0                                    |1      |
|shift_pll:inst|altpll:altpll_component|pll|1      |
+------------------------------------------+-------+

+-----------------------------------------------------------------------------+
|PLL Summary                                                                  |
+-----------------------------------------------------------------------------+
+----------------------------+------------------------------------------+
|PLL Property                |shift_pll:inst|altpll:altpll_component|pll|
+----------------------------+------------------------------------------+
|PLL type                    |Enhanced                                  |
|Scan chain                  |None                                      |
|PLL mode                    |Normal                                    |
|Feedback source             |-                                         |
|Compensate clock            |clock0                                    |
|Switchover on loss of clock |Off                                       |
|Switchover on gated lock    |Off                                       |
|Switchover counter          |-                                         |
|Primary clock               |inclk0                                    |
|Input frequency 0           |100.0 MHz                                 |
|Input frequency 1           |-                                         |
|Nominal VCO frequency       |400.0 MHz                                 |
|Freq min lock               |75.01 MHz                                 |
|Freq max lock               |250.0 MHz                                 |
|Hold conf done              |Off                                       |
|M value                     |4                                         |
|N value                     |1                                         |
|M counter delay             |0 ps                                      |
|N counter delay             |0 ps                                      |
|M2 value                    |-                                         |
|N2 value                    |-                                         |
|SS counter                  |-                                         |
|Downspread                  |-                                         |
|Spread frequency            |-                                         |
|Charge pump current         |50 uA                                     |
|Loop filter resistance      |1.02 KOhm                                 |
|Loop filter capacitance     |10 pF                                     |
|Freq zero                   |1.51 MHz                                  |
|Bandwidth                   |20 MHz                                    |
|Freq pole                   |99.5 MHz                                  |
|enable0 counter             |-                                         |
|enable1 counter             |-                                         |
|Real time reconfigurable    |Off                                       |
|Bit stream for reprogramming|-                                         |
+----------------------------+------------------------------------------+

+-----------------------------------------------------------------------------+
|PLL Usage                                                                    |
+-----------------------------------------------------------------------------+
+--------------------------------------------+------------+----+---+----------------+-----------+-------+----------+-------+-------------+-------------+----------+-------+-------+
|Name                                        |Output Clock|Mult|Div|Output Frequency|Phase Shift|Delay  |Duty Cycle|Counter|Counter Delay|Counter Value|High / Low|Initial|VCO Tap|
+--------------------------------------------+------------+----+---+----------------+-----------+-------+----------+-------+-------------+-------------+----------+-------+-------+
|shift_pll:inst|altpll:altpll_component|_clk0|clock0      |4   |3  |133.33 MHz      |0 (0 ps)   |0 ps   |50/50     |G3     |0 ps         |3            |2/1 Odd   |1      |0      |
|shift_pll:inst|altpll:altpll_component|_clk1|clock1      |2   |1  |200.0 MHz       |0 (0 ps)   |0 ps   |50/50     |G2     |0 ps         |2            |1/1 Even  |1      |0      |
|shift_pll:inst|altpll:altpll_component|_clk2|clock2      |2   |1  |200.0 MHz       |0 (0 ps)   |1000 ps|50/50     |G1     |1000 ps      |2            |1/1 Even  |1      |0      |
+--------------------------------------------+------------+----+---+----------------+-----------+-------+----------+-------+-------------+-------------+----------+-------+-------+

+-----------------------------------------------------------------------------+
|Interconnect Usage Summary                                                   |
+-----------------------------------------------------------------------------+
+---------------------------+--------------------+
|Interconnect Resource Type |Usage               |
+---------------------------+--------------------+
|C16 interconnects          |0 / 2,286 ( 0 % )   |
|C4 interconnects           |1 / 31,320 ( < 1 % )|
|C8 interconnects           |0 / 7,272 ( 0 % )   |
|DIFFIOCLKs                 |0 / 16 ( 0 % )      |
|DQS I/O buses              |0 / 16 ( 0 % )      |
|Direct links               |2 / 44,710 ( < 1 % )|
|Fast regional clocks       |0 / 8 ( 0 % )       |
|Global clocks              |3 / 16 ( 18 % )     |
|I/O buses                  |1 / 208 ( < 1 % )   |
|Local routing interconnects|3 / 10,570 ( < 1 % )|
|R24 interconnects          |0 / 2,280 ( 0 % )   |
|R4 interconnects           |0 / 62,520 ( 0 % )  |
|R8 interconnects           |0 / 10,410 ( 0 % )  |
|Regional clocks            |0 / 16 ( 0 % )      |
+---------------------------+--------------------+

+-----------------------------------------------------------------------------+
|LAB Logic Elements                                                           |
+-----------------------------------------------------------------------------+
+----------------------------------------+---------------------------+
|Number of Logic Elements  (Average = 1.)|Number of LABs  (Total = 3)|
+----------------------------------------+---------------------------+
|1                                       |3                          |
|2                                       |0                          |
|3                                       |0                          |
|4                                       |0                          |
|5                                       |0                          |
|6                                       |0                          |
|7                                       |0                          |
|8                                       |0                          |
|9                                       |0                          |
|10                                      |0                          |
+----------------------------------------+---------------------------+

+-----------------------------------------------------------------------------+
|LAB-wide Signals                                                             |
+-----------------------------------------------------------------------------+
+--------------------------------+---------------------------+
|LAB-wide Signals  (Average = 1.)|Number of LABs  (Total = 3)|
+--------------------------------+---------------------------+
|1 Clock                         |3                          |
+--------------------------------+---------------------------+

+-----------------------------------------------------------------------------+
|LAB Signals Sourced                                                          |
+-----------------------------------------------------------------------------+
+-----------------------------------------+---------------------------+
|Number of Signals Sourced  (Average = 1.)|Number of LABs  (Total = 3)|
+-----------------------------------------+---------------------------+
|0                                        |0                          |
|1                                        |3                          |
+-----------------------------------------+---------------------------+

+-----------------------------------------------------------------------------+
|LAB Signals Sourced Out                                                      |
+-----------------------------------------------------------------------------+
+---------------------------------------------+---------------------------+
|Number of Signals Sourced Out  (Average = 1.)|Number of LABs  (Total = 3)|
+---------------------------------------------+---------------------------+
|0                                            |0                          |
|1                                            |3                          |
+---------------------------------------------+---------------------------+

+-----------------------------------------------------------------------------+
|LAB Distinct Inputs                                                          |
+-----------------------------------------------------------------------------+
+-----------------------------------------+---------------------------+
|Number of Distinct Inputs  (Average = 1.)|Number of LABs  (Total = 3)|
+-----------------------------------------+---------------------------+
|0                                        |0                          |
|1                                        |3                          |
+-----------------------------------------+---------------------------+

+-----------------------------------------------------------------------------+
|Timing Settings                                                              |
+-----------------------------------------------------------------------------+
+---------------+-----------+----------------+----------------------------------------------------------------+------------------+
|Assignment File|Source Name|Destination Name|Option                                                          |Setting           |
+---------------+-----------+----------------+----------------------------------------------------------------+------------------+
|shift_clk.psf  |Include external delays to/from device pins in fmax calculations|Off               |
|shift_clk.psf  |Run All Timing Analyses                                         |Off               |
|shift_clk.psf  |Ignore user-defined clock settings                              |Off               |
|shift_clk.psf  |Default hold multicycle                                         |Same As Multicycle|
|shift_clk.psf  |Cut off feedback from I/O pins                                  |On                |
|shift_clk.psf  |Cut off clear and preset signal paths                           |On                |
|shift_clk.psf  |Cut off read during write signal paths                          |On                |
|shift_clk.psf  |Cut paths between unrelated clock domains                       |On                |
|shift_clk.psf  |Number of paths to report                                       |200               |
|shift_clk.psf  |Number of destination nodes to report                           |10                |
|shift_clk.psf  |Number of source nodes to report per destination node           |10                |
|shift_clk.psf  |Maximum Strongly Connected Component loop size                  |50                |
|Device name                                                     |EP1S10F780C7      |
+---------------+-----------+----------------+----------------------------------------------------------------+------------------+

+-----------------------------------------------------------------------------+
|Clock Requirement: 'shift_pll:inst|altpll:altpll_component|_clk0' ( 133.33 MHz, -1.437 ns )|
+-----------------------------------------------------------------------------+
+-----------+----------------+--------------------------------------------+--------------------------------------------+---------------------------+-------------------------+-----------------------+--------+
|Source Name|Destination Name|Source Clock Name                           |Destination Clock Name                      |Required Setup Relationship|Required Longest P2P Time|Actual Longest P2P Time|Slack   |
+-----------+----------------+--------------------------------------------+--------------------------------------------+---------------------------+-------------------------+-----------------------+--------+
|inst2      |inst2           |shift_pll:inst|altpll:altpll_component|_clk0|shift_pll:inst|altpll:altpll_component|_clk0|7.500 ns                   |7.287 ns                 |0.737 ns               |6.550 ns|
+-----------+----------------+--------------------------------------------+--------------------------------------------+---------------------------+-------------------------+-----------------------+--------+

+-----------------------------------------------------------------------------+
|Clock Requirement: 'shift_pll:inst|altpll:altpll_component|_clk1' ( 200.0 MHz, -1.437 ns )|
+-----------------------------------------------------------------------------+
+-----------+----------------+--------------------------------------------+--------------------------------------------+---------------------------+-------------------------+-----------------------+--------+
|Source Name|Destination Name|Source Clock Name                           |Destination Clock Name                      |Required Setup Relationship|Required Longest P2P Time|Actual Longest P2P Time|Slack   |
+-----------+----------------+--------------------------------------------+--------------------------------------------+---------------------------+-------------------------+-----------------------+--------+
|inst4      |inst4           |shift_pll:inst|altpll:altpll_component|_clk1|shift_pll:inst|altpll:altpll_component|_clk1|5.000 ns                   |4.787 ns                 |0.737 ns               |4.050 ns|
+-----------+----------------+--------------------------------------------+--------------------------------------------+---------------------------+-------------------------+-----------------------+--------+

+-----------------------------------------------------------------------------+
|Clock Requirement: 'shift_pll:inst|altpll:altpll_component|_clk2' ( 200.0 MHz, -437 ps )|
+-----------------------------------------------------------------------------+
+-----------+----------------+--------------------------------------------+--------------------------------------------+---------------------------+-------------------------+-----------------------+--------+
|Source Name|Destination Name|Source Clock Name                           |Destination Clock Name                      |Required Setup Relationship|Required Longest P2P Time|Actual Longest P2P Time|Slack   |
+-----------+----------------+--------------------------------------------+--------------------------------------------+---------------------------+-------------------------+-----------------------+--------+
|inst5      |inst5           |shift_pll:inst|altpll:altpll_component|_clk2|shift_pll:inst|altpll:altpll_component|_clk2|5.000 ns                   |4.787 ns                 |0.737 ns               |4.050 ns|
+-----------+----------------+--------------------------------------------+--------------------------------------------+---------------------------+-------------------------+-----------------------+--------+

+-----------------------------------------------------------------------------+
|tco (Clock to Output Delays)                                                 |
+-----------------------------------------------------------------------------+
+-------------------+------------+----------+
|Output Name        |Required tco|Actual tco|
|   -- Register Name|            |          |
|      -- Clock Name|            |          |
+-------------------+------------+----------+
|tff2               |None        |6.676 ns  |
|   -- inst5        |None        |6.676 ns  |
|      -- inclk0    |None        |6.676 ns  |
|tff0               |None        |5.436 ns  |
|   -- inst2        |None        |5.436 ns  |
|      -- inclk0    |None        |5.436 ns  |
|tff1               |None        |5.436 ns  |
|   -- inst4        |None        |5.436 ns  |
|      -- inclk0    |None        |5.436 ns  |
+-------------------+------------+----------+

+-----------------------------------------------------------------------------+
|Processing Time                                                              |
+-----------------------------------------------------------------------------+
+-----------------+------------+
|Module Name      |Elapsed Time|
+-----------------+------------+
|Database Builder |00:00:03    |
|Logic Synthesizer|00:00:00    |
|Fitter           |00:00:47    |
|Assembler        |00:00:00    |
|Delay Annotator  |00:00:04    |
|Timing Analyzer  |00:00:00    |
|Total            |00:00:57    |
+-----------------+------------+