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📄 shift_clk.csf.rpt

📁 vhdl编写的一个完整工程
💻 RPT
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+-----------------------------------------------------------------------------+
|Resource Usage Summary                                                       |
+-----------------------------------------------------------------------------+
+------------------------+--------------------------------------------+
|Resource                |Usage                                       |
+------------------------+--------------------------------------------+
|Logic cells             |3 / 10,570 ( < 1 % )                        |
|Flipflops               |3 / 11,848 ( < 1 % )                        |
|I/O pins                |5 / 426 ( 1 % )                             |
|Clock pins              |1                                           |
|Dedicated input pins    |0                                           |
|Global signals          |1                                           |
|M512s                   |0 / 94 ( 0 % )                              |
|M4Ks                    |0 / 60 ( 0 % )                              |
|MegaRAMs                |0 / 1 ( 0 % )                               |
|Total memory bits       |0 / 920,448 ( 0 % )                         |
|DSP block 9-bit elements|0 / 48 ( 0 % )                              |
|PLLs                    |1 / 6 ( 16 % )                              |
|Global clocks           |3 / 16 ( 18 % )                             |
|Regional clocks         |0 / 16 ( 0 % )                              |
|Fast regional clocks    |0 / 8 ( 0 % )                               |
|DIFFIOCLKs              |0 / 16 ( 0 % )                              |
|SERDES transmitters     |0 / 44 ( 0 % )                              |
|SERDES receivers        |0 / 44 ( 0 % )                              |
|Maximum fan-out node    |shift_pll:inst|altpll:altpll_component|_clk0|
|Maximum fan-out         |4                                           |
|Total fan-out           |11                                          |
|Average fan-out         |1.2                                         |
+------------------------+--------------------------------------------+

+-----------------------------------------------------------------------------+
|Input Pins                                                                   |
+-----------------------------------------------------------------------------+
+------+-----+------------+------------+-----------+---------------------+------------------+------+--------------+-------------+--------------+-----------+---------------+--------+------------+---------+------------+--------------------------+
|Name  |Pin #|X coordinate|Y coordinate|Cell number|Combinational Fan-Out|Registered Fan-Out|Global|Input Register|Power Up High|Slow Slew Rate|Delay Chain|PCI I/O Enabled|Bus Hold|Weak Pull Up|Turbo Bit|I/O Standard|OCT and Impedance Matching|
+------+-----+------------+------------+-----------+---------------------+------------------+------+--------------+-------------+--------------+-----------+---------------+--------+------------+---------+------------+--------------------------+
|inclk0|K17  |21          |31          |2          |1                    |0                 |no    |no            |no           |no            |no         |no             |no      |Off         |no       |LVTTL       |Off                       |
+------+-----+------------+------------+-----------+---------------------+------------------+------+--------------+-------------+--------------+-----------+---------------+--------+------------+---------+------------+--------------------------+

+-----------------------------------------------------------------------------+
|Output Pins                                                                  |
+-----------------------------------------------------------------------------+
+------+-----+------------+------------+-----------+---------------+----------------------+-------------+--------------+---------------+---------------+----------+--------+------------+---------+------------+----------------+--------------------------+
|Name  |Pin #|X coordinate|Y coordinate|Cell number|Output Register|Output Enable Register|Power Up High|Slow Slew Rate|TCO Delay Chain|PCI I/O Enabled|Open Drain|Bus Hold|Weak Pull Up|Turbo Bit|I/O Standard|Current Strength|OCT and Impedance Matching|
+------+-----+------------+------------+-----------+---------------+----------------------+-------------+--------------+---------------+---------------+----------+--------+------------+---------+------------+----------------+--------------------------+
|locked|L13  |29          |31          |0          |no             |no                    |no           |no            |no             |no             |no        |no      |Off         |no       |LVTTL       |24mA            |Off                       |
|tff0  |V27  |0           |9           |2          |no             |no                    |no           |no            |no             |no             |no        |no      |Off         |no       |LVTTL       |24mA            |Off                       |
|tff1  |Y26  |0           |4           |2          |no             |no                    |no           |no            |no             |no             |no        |no      |Off         |no       |LVTTL       |24mA            |Off                       |
|tff2  |B18  |17          |31          |3          |no             |no                    |no           |no            |no             |no             |no        |no      |Off         |no       |LVTTL       |24mA            |Off                       |
+------+-----+------------+------------+-----------+---------------+----------------------+-------------+--------------+---------------+---------------+----------+--------+------------+---------+------------+----------------+--------------------------+

+-----------------------------------------------------------------------------+
|All Package Pins                                                             |
+-----------------------------------------------------------------------------+
+-----+-------------+------------+
|Pin #|Usage        |I/O Standard|
+-----+-------------+------------+
|G27  |GND*         |
|G28  |GND*         |
|K21  |GND*         |
|K22  |GND*         |
|H26  |GND*         |
|H25  |GND*         |
|L22  |GND*         |
|L21  |GND*         |
|H27  |GND*         |
|H28  |GND*         |
|L23  |GND*         |
|L24  |GND*         |
|E24  |GND          |
|J25  |GND*         |
|J26  |GND*         |
|L20  |GND*         |
|L19  |GND*         |
|J27  |GND*         |
|J28  |GND*         |
|M22  |GND*         |
|M21  |GND*         |
|K26  |GND*         |
|K25  |GND*         |
|M24  |GND*         |
|M23  |GND*         |
|K27  |GND*         |
|K28  |GND*         |
|M20  |GND*         |
|M19  |GND*         |
|L25  |GND*         |
|L26  |GND*         |
|N26  |GND*         |
|N25  |GND*         |
|L27  |GND*         |
|L28  |GND*         |
|N24  |GND*         |
|N23  |GND*         |
|K20  |GND          |
|M25  |GND*         |
|M26  |GND*         |
|N22  |GND*         |
|N21  |GND*         |
|M27  |GND*         |
|N28  |GND*         |
|N20  |GND*         |
|N19  |GND*         |
|N27  |GND+         |
|P27  |GND+         |
|P26  |GND*         |
|P25  |GND+         |
|P23  |VCCA_PLL1    |
|P24  |GNDA_PLL1    |
|P21  |VCCG_PLL1    |
|P22  |GNDG_PLL1    |
|R23  |VCCA_PLL2    |
|R24  |GNDA_PLL2    |
|R21  |VCCG_PLL2    |
|R22  |GNDG_PLL2    |
|R27  |GND+         |
|T27  |GND+         |
|R25  |GND+         |
|R26  |GND*         |
|T28  |GND*         |
|U27  |GND*         |
|T21  |GND*         |
|T22  |GND*         |
|U26  |GND*         |
|U25  |GND*         |
|T19  |GND*         |
|T20  |GND*         |
|R19  |GND          |
|V27  |tff0         |LVTTL       |
|V28  |GND*         |
|T23  |GND*         |
|T24  |GND*         |
|V26  |GND*         |
|V25  |GND*         |
|T26  |GND*         |
|T25  |GND*         |
|W28  |GND*         |
|W27  |GND*         |
|U19  |GND*         |
|U20  |GND*         |
|W26  |GND*         |
|W25  |GND*         |
|U24  |GND*         |
|U23  |GND*         |
|Y28  |GND*         |
|Y27  |GND*         |
|U21  |GND*         |
|U22  |GND*         |
|Y26  |tff1         |LVTTL       |
|Y25  |GND*         |
|V19  |GND*         |
|V20  |GND*         |
|W20  |GND          |
|AA28 |GND*         |
|AA27 |GND*         |
|V24  |GND*         |
|V23  |GND*         |
|AA25 |GND*         |
|AA26 |GND*         |
|V22  |GND*         |
|V21  |GND*         |
|AB28 |GND*         |
|AB27 |GND*         |
|W23  |GND*         |
|W24  |GND*         |
|AG26 |GND*         |
|AH26 |GND*         |
|AG25 |GND*         |
|AH25 |GND*         |
|AF25 |GND*         |
|AF24 |GND*         |
|AG24 |GND*         |
|AG23 |GND*         |
|AE24 |GND*         |
|AD23 |GND*         |
|AH24 |GND*         |
|AF23 |GND*         |
|AD22 |GND          |
|AH23 |GND*         |
|AE22 |GND*         |
|AE23 |GND*         |
|AF22 |GND*         |
|AH22 |GND*         |
|AG22 |GND*         |
|AB18 |GND*         |
|AD21 |GND*         |
|AE21 |GND*         |
|AG21 |GND*         |
|AF21 |GND*         |
|AE20 |GND*         |
|AG20 |GND*         |
|AF20 |GND*         |
|AH21 |GND*         |
|AH20 |GND*         |
|V18  |GND*         |
|AE19 |GND*         |
|AD19 |GND*         |
|AF19 |GND*         |
|AG19 |GND*         |
|AB19 |GND*         |
|AC21 |GND*         |
|AC19 |GND*         |
|AH19 |GND*         |
|AF18 |GND*         |
|AD18 |GND*         |
|AA20 |GND*         |
|AE18 |GND*         |
|AG18 |GND*         |
|Y19  |GND*         |
|W19  |GND*         |
|W18  |GND*         |
|AA19 |GND*         |
|Y18  |GND*         |
|AA18 |GND*         |
|AD20 |GND          |
|Y17  |GND*         |
|AA17 |GND+         |
|AB17 |GND*         |
|AC17 |GND+         |
|AC18 |PLL_ENA      |
|AC16 |^MSEL0       |
|W17  |^MSEL1       |
|AB15 |^MSEL2       |
|Y16  |GND*         |
|W16  |GND*         |
|AG15 |GND*         |
|AF15 |GND*         |
|AA15 |GND*         |
|AA14 |GND*         |
|W15  |GND*         |
|W14  |GND*         |
|AE15 |GND*         |
|AD15 |GND*         |
|AB16 |VCC_PLL6_OUTB|
|AC14 |VCC_PLL6_OUTA|
|AG14 |VCCA_PLL6    |
|AF14 |GNDA_PLL6    |
|AA13 |VCCG_PLL6    |
|AB14 |GNDG_PLL6    |
|W13  |GND+         |
|Y13  |GND*         |
|AD14 |GND+         |
|AE14 |GND*         |
|AB13 |^nCE         |
|AC13 |^nCE         |
|Y9   |GND*         |
|AE4  |GND*         |
|W12  |GND*         |
|Y12  |^nIO_PULLUP  |
|AA12 |^VCCSEL      |
|AC12 |^PORSEL      |
|W11  |GND*         |
|AC11 |GND*         |
|W10  |GND*         |
|AA11 |GND*         |
|AC10 |GND*         |
|AB11 |GND*         |
|AD11 |GND          |
|AG11 |GND*         |
|AH11 |GND*         |
|AE11 |GND*         |
|AC9  |GND*         |
|AF11 |GND*         |
|AE10 |GND*         |
|AG10 |GND*         |
|AH10 |GND*         |
|AF10 |GND*         |
|AD10 |GND*         |
|AC8  |GND*         |
|AB10 |GND*         |
|AG9  |GND*         |
|AF9  |GND*         |
|AE9  |GND*         |

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