📄 shift_clk.csf.rpt
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shift_clk - Quartus II Compilation Report File
-------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------------------------------------+
|Report Information |
+------------------+----------------------------------------------------------------------------------------------------------+
|Project |D:\Data\Technical Marketing\Yeager\MFUG\examples\altpll\complete_project\shift_clk\db\shift_clk.quartus_db|
|Compiler Settings |shift_clk |
|Quartus II Version|2.0 Build 204 03/26/2002 SP 1 |
+------------------+----------------------------------------------------------------------------------------------------------+
Table of Contents
Compilation Report
Legal Notice
Project Settings
General Settings
Results for "shift_clk" Compiler Settings
Summary
Compiler Settings
Messages
Hierarchy
Post-Synthesis Resource Utilization by Entity
Device Options
Equations
Floorplan View
Pin-Out File
Resource Section
Resource Usage Summary
Input Pins
Output Pins
All Package Pins
Control Signals
Global & Other Fast Signals
Non-Global High Fan-Out Signals
PLL Summary
PLL Usage
LAB and Routing Section
Interconnect Usage Summary
LAB Logic Elements
LAB-wide Signals
LAB Signals Sourced
LAB Signals Sourced Out
LAB Distinct Inputs
Timing Analyses
Timing Settings
Clock Requirement: 'shift_pll:inst|altpll:altpll_component|_clk0' ( 133.33 MHz, -1.437 ns )
Clock Requirement: 'shift_pll:inst|altpll:altpll_component|_clk1' ( 200.0 MHz, -1.437 ns )
Clock Requirement: 'shift_pll:inst|altpll:altpll_component|_clk2' ( 200.0 MHz, -437 ps )
tco (Clock to Output Delays)
Processing Time
+-----------------------------------------------------------------------------+
|Legal Notice |
+-----------------------------------------------------------------------------+
Copyright (C) 1991-2002 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+-----------------------------------------------------------------------------+
|General Settings |
+-----------------------------------------------------------------------------+
+-----------------+-------------------+
|Option |Setting |
+-----------------+-------------------+
|Start date & time|06/20/2002 09:20:04|
|Main task |Compilation |
|Settings name |shift_clk |
+-----------------+-------------------+
+-----------------------------------------------------------------------------+
|Summary |
+-----------------------------------------------------------------------------+
+-----------------------------------+---------------------------------------------+
|Processing status |Fitting Successful - Thu Jun 20 09:21:09 2002|
|Timing requirements/analysis status|Requirements met |
|Chip name |shift_clk |
|Device name |EP1S10F780C7 |
|Total logic elements |3 / 10,570 ( < 1 % ) |
|Total pins |5 / 426 ( 1 % ) |
|Total memory bits |0 / 920,448 ( 0 % ) |
|DSP block 9-bit elements |0 / 48 ( 0 % ) |
+-----------------------------------+---------------------------------------------+
+-----------------------------------------------------------------------------+
|Compiler Settings |
+-----------------------------------------------------------------------------+
+------------------------------------------+------------------+
|Option |Setting |
+------------------------------------------+------------------+
|Chip name |shift_clk |
|Family name |Stratix |
|Focus entity name ||shift_clk |
|Device |EP1S10F780C7 |
|Compilation mode |Full |
|Disk space/compilation speed tradeoff |Normal |
|Preserve fewer node names |On |
|Optimize timing |Normal Compilation|
|Optimize IOC register placement for timing|On |
|Generate timing analyses |On |
|Fast Fit compilation |Off |
|SignalProbe compilation |Off |
+------------------------------------------+------------------+
+-----------------------------------------------------------------------------+
|Messages |
+-----------------------------------------------------------------------------+
Info: Found 1 design units and 1 entities in source file D:\Data\Technical Marketing\Yeager\MFUG\examples\altpll\complete_project\shift_clk\shift_clk.bdf
Info: Found entity 1: shift_clk
Info: Found 0 design units and 0 entities in source file D:\Data\Technical Marketing\Yeager\MFUG\examples\altpll\complete_project\shift_clk\shift_clk.vwf
Info: Found 1 design units and 1 entities in source file D:\Data\Technical Marketing\Yeager\MFUG\examples\altpll\complete_project\shift_clk\shift_pll.tdf
Info: Found entity 1: shift_pll
Info: Found 1 design units and 1 entities in source file D:\quartus_20\libraries\megafunctions\altpll.tdf
Info: Found entity 1: altpll
Info: Implemented 9 device resources
Info: Implemented 1 input pins
Info: Implemented 4 output pins
Info: Implemented 3 logic cells
Info: Implemented 1 ClockLock PLLs
Info: Selected device EP1S10F780C7 for design shift_clk
Info: Chose type Enhanced for Auto type PLL shift_pll:inst|altpll:altpll_component|_clk0
Info: Can implement multiplication and division for ClockLock PLL shift_pll:inst|altpll:altpll_component|_clk0
Info: Implementing clock multiplication of 4, clock division of 3, and phase shift of 0 degrees (0 ps) for shift_pll:inst|altpll:altpll_component|_clk0 port
Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for shift_pll:inst|altpll:altpll_component|_clk1 port
Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for shift_pll:inst|altpll:altpll_component|_clk2 port
Info: Compilation Report contains advance information. Specifications for device EP1S10F780C7 are subject to change. Contact Altera for information on availability. No programming file will be generated.
Warning: Timing characteristics of device EP1S10F780C7 are preliminary
Info: Found complex timing assignments. Calculating slack delays instead of fmax.
Info: Slack time is 6.55 ns for clock shift_pll:inst|altpll:altpll_component|_clk0 between source register inst2 and destination register inst2
Info: + Largest register to register requirement is 7.287 ns
Info: + Setup relationship between source and destination is 7.500 ns
Info: + Latch edge is 6.063 ns
Info: Clock period of Destination clock shift_pll:inst|altpll:altpll_component|_clk0 is 7.500 ns with offset of -1.437 ns
Info: Multicycle Setup factor for Destination register is 1
Info: - Launch edge is -1.437 ns
Info: Clock period of Source clock shift_pll:inst|altpll:altpll_component|_clk0 is 7.500 ns with offset of -1.437 ns
Info: Multicycle Setup factor for Source register is 1
Info: + Largest clock skew is 0.000 ns
Info: + Shortest clock path from clock shift_pll:inst|altpll:altpll_component|_clk0 to destination register is 2.335 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_X27_Y31_N0; CLK Node = 'shift_pll:inst|altpll:altpll_component|_clk0'
Info: 2: + IC(1.691 ns) + CELL(0.644 ns) = 2.335 ns; Loc. = LC_X1_Y9_N2; REG Node = 'inst2'
Info: - Longest clock path from clock shift_pll:inst|altpll:altpll_component|_clk0 to source register is 2.335 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_X27_Y31_N0; CLK Node = 'shift_pll:inst|altpll:altpll_component|_clk0'
Info: 2: + IC(1.691 ns) + CELL(0.644 ns) = 2.335 ns; Loc. = LC_X1_Y9_N2; REG Node = 'inst2'
Info: - Micro clock to output delay of source is 0.202 ns
Info: - Micro setup delay of destination is 0.011 ns
Info: - Longest register to register delay is 0.737 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y9_N2; REG Node = 'inst2'
Info: 2: + IC(0.467 ns) + CELL(0.270 ns) = 0.737 ns; Loc. = LC_X1_Y9_N2; REG Node = 'inst2'
Info: Slack time is 4.05 ns for clock shift_pll:inst|altpll:altpll_component|_clk1 between source register inst4 and destination register inst4
Info: + Largest register to register requirement is 4.787 ns
Info: + Setup relationship between source and destination is 5.000 ns
Info: + Latch edge is 3.563 ns
Info: Clock period of Destination clock shift_pll:inst|altpll:altpll_component|_clk1 is 5.000 ns with offset of -1.437 ns
Info: Multicycle Setup factor for Destination register is 1
Info: - Launch edge is -1.437 ns
Info: Clock period of Source clock shift_pll:inst|altpll:altpll_component|_clk1 is 5.000 ns with offset of -1.437 ns
Info: Multicycle Setup factor for Source register is 1
Info: + Largest clock skew is 0.000 ns
Info: + Shortest clock path from clock shift_pll:inst|altpll:altpll_component|_clk1 to destination register is 2.335 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_X27_Y31_N0; CLK Node = 'shift_pll:inst|altpll:altpll_component|_clk1'
Info: 2: + IC(1.691 ns) + CELL(0.644 ns) = 2.335 ns; Loc. = LC_X1_Y4_N2; REG Node = 'inst4'
Info: - Longest clock path from clock shift_pll:inst|altpll:altpll_component|_clk1 to source register is 2.335 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_X27_Y31_N0; CLK Node = 'shift_pll:inst|altpll:altpll_component|_clk1'
Info: 2: + IC(1.691 ns) + CELL(0.644 ns) = 2.335 ns; Loc. = LC_X1_Y4_N2; REG Node = 'inst4'
Info: - Micro clock to output delay of source is 0.202 ns
Info: - Micro setup delay of destination is 0.011 ns
Info: - Longest register to register delay is 0.737 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y4_N2; REG Node = 'inst4'
Info: 2: + IC(0.467 ns) + CELL(0.270 ns) = 0.737 ns; Loc. = LC_X1_Y4_N2; REG Node = 'inst4'
Info: Slack time is 4.05 ns for clock shift_pll:inst|altpll:altpll_component|_clk2 between source register inst5 and destination register inst5
Info: + Largest register to register requirement is 4.787 ns
Info: + Setup relationship between source and destination is 5.000 ns
Info: + Latch edge is 4.563 ns
Info: Clock period of Destination clock shift_pll:inst|altpll:altpll_component|_clk2 is 5.000 ns with offset of -0.437 ns
Info: Multicycle Setup factor for Destination register is 1
Info: - Launch edge is -0.437 ns
Info: Clock period of Source clock shift_pll:inst|altpll:altpll_component|_clk2 is 5.000 ns with offset of -0.437 ns
Info: Multicycle Setup factor for Source register is 1
Info: + Largest clock skew is 0.000 ns
Info: + Shortest clock path from clock shift_pll:inst|altpll:altpll_component|_clk2 to destination register is 2.335 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_X27_Y31_N0; CLK Node = 'shift_pll:inst|altpll:altpll_component|_clk2'
Info: 2: + IC(1.691 ns) + CELL(0.644 ns) = 2.335 ns; Loc. = LC_X17_Y30_N2; REG Node = 'inst5'
Info: - Longest clock path from clock shift_pll:inst|altpll:altpll_component|_clk2 to source register is 2.335 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_X27_Y31_N0; CLK Node = 'shift_pll:inst|altpll:altpll_component|_clk2'
Info: 2: + IC(1.691 ns) + CELL(0.644 ns) = 2.335 ns; Loc. = LC_X17_Y30_N2; REG Node = 'inst5'
Info: - Micro clock to output delay of source is 0.202 ns
Info: - Micro setup delay of destination is 0.011 ns
Info: - Longest register to register delay is 0.737 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y30_N2; REG Node = 'inst5'
Info: 2: + IC(0.467 ns) + CELL(0.270 ns) = 0.737 ns; Loc. = LC_X17_Y30_N2; REG Node = 'inst5'
Info: All timing requirements were met. See Report window for more details.
Info: Design shift_clk: Full compilation was successful. 0 errors, 1 warning
+-----------------------------------------------------------------------------+
|Hierarchy |
+-----------------------------------------------------------------------------+
CompileHierarchy
shift_clk
shift_pll:inst
altpll:altpll_component
+-----------------------------------------------------------------------------+
|Post-Synthesis Resource Utilization by Entity |
+-----------------------------------------------------------------------------+
+-------------------------------+-----------+---------+---------------+------------+----+-------------------------------------------------+
|Compilation Hierarchy Node |Logic Cells|Registers|Memory Segments|DSP Elements|Pins|Full Hierarchy Name |
+-------------------------------+-----------+---------+---------------+------------+----+-------------------------------------------------+
||shift_clk |3 |3 |0 |0 |5 ||shift_clk |
| |shift_pll:inst| |0 |0 |0 |0 |0 ||shift_clk|shift_pll:inst |
| |altpll:altpll_component||0 |0 |0 |0 |0 ||shift_clk|shift_pll:inst|altpll:altpll_component|
+-------------------------------+-----------+---------+---------------+------------+----+-------------------------------------------------+
+-----------------------------------------------------------------------------+
|Device Options |
+-----------------------------------------------------------------------------+
+----------------------------------------------------------------+------------------------+
|Option |Setting |
+----------------------------------------------------------------+------------------------+
|Auto-restart configuration after error |Off |
|Release clears before tri-states |Off |
|Enable user-supplied start-up clock (CLKUSR) |Off |
|Enable device-wide reset (DEV_CLRn) |Off |
|Enable device-wide output enable (DEV_OE) |Off |
|Enable INIT_DONE output |Off |
|Auto-increment JTAG user code for multiple configuration devices|On |
|Disable CONF_DONE and nSTATUS pull-ups on configuration device |Off |
|Generate Tabular Text File (.ttf) |Off |
|Generate Raw Binary File (.rbf) |Off |
|Generate Hexadecimal Output File (.hexout) |Off |
|Configuration scheme |Passive Serial |
|Hexadecimal Output File count direction |Up |
|JTAG user code for target device |0XFFFFFFFF |
|JTAG user code for configuration device |0XFFFFFFFF |
|Hexadecimal Output File start address |0 |
|Reserve all unused pins |As output driving ground|
|Configuration device |EPC2 |
|Use check sum as user code |Off |
|Use check sum as user code for EPROM |Off |
+----------------------------------------------------------------+------------------------+
+-----------------------------------------------------------------------------+
|Equations |
+-----------------------------------------------------------------------------+
The equations can be found in D:\Data\Technical Marketing\Yeager\MFUG\examples\altpll\complete_project\shift_clk\shift_clk.eqn.
+-----------------------------------------------------------------------------+
|Floorplan View |
+-----------------------------------------------------------------------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.
+-----------------------------------------------------------------------------+
|Pin-Out File |
+-----------------------------------------------------------------------------+
The pin-out file can be found in D:\Data\Technical Marketing\Yeager\MFUG\examples\altpll\complete_project\shift_clk\shift_clk.pin.
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