ddr_clk.csf.msg

vhdl编写的一个完整工程

{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\ddr_clk\\DDR_CLK.bdf " "Found 1 design units and 1 entities in source file D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\ddr_clk\\DDR_CLK.bdf" { { Info "ISGN_ENTITY_NAME" "1 DDR_CLK " "Found entity 1: DDR_CLK" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\ddr_clk\\DDR_CLK.bdf" "DDR_CLK" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\ddr_clk\\DDR_CLK.bdf" { { } } } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "0 0 D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\ddr_clk\\DDR_CLK.vwf " "Found 0 design units and 0 entities in source file D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\ddr_clk\\DDR_CLK.vwf" {  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\ddr_clk\\ddr_pll.tdf " "Found 1 design units and 1 entities in source file D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\ddr_clk\\ddr_pll.tdf" { { Info "ISGN_ENTITY_NAME" "1 ddr_pll " "Found entity 1: ddr_pll" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\ddr_clk\\ddr_pll.tdf" "ddr_pll" "" { Text "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\ddr_clk\\ddr_pll.tdf" 40 1 0 } }  } }  } {  }  }
{  Info "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "1 1 D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf " "Found 1 design units and 1 entities in source file D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" { { Info "ISGN_ENTITY_NAME" "1 altpll " "Found entity 1: altpll" {  } { { "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" "altpll" "" { Text "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" 268 1 0 } }  } }  } {  }  }
{  Info "ISCL_SCL_TM_SUMMARY" "8 " "Implemented 8 device resources" { { Info "ISCL_SCL_TM_IPINS" "2 " "Implemented 2 input pins" {  } {  } } { Info "ISCL_SCL_TM_OPINS" "5 " "Implemented 5 output pins" {  } {  } } { Info "ISCL_SCL_TM_PLLS" "1 " "Implemented 1 ClockLock PLLs" {  } {  } }  } {  }  }
{  Info "IMPP_MPP_USER_DEVICE" "EP1S10F780C7 DDR_CLK " "Selected device EP1S10F780C7 for design DDR_CLK" {  } {  }  }
{  Info "ICUT_CUT_YGR_PLL_SET_PLL_COMPENSATE" "e0 extclk0 ddr_pll:inst\|altpll:altpll_component\|pll " "Compensating output pin e0, which is fed by extclk0 port of enhanced PLL ddr_pll:inst\|altpll:altpll_component\|pll" {  } { { "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\ddr_clk\\DDR_CLK.bdf" "" "" { Schematic "D:\\Data\\Technical Marketing\\Yeager\\MFUG\\examples\\altpll\\complete_project\\ddr_clk\\DDR_CLK.bdf" { { { 72 576 752 88 "e0" "" } { 64 504 576 80 "e0" "" } } } } } { "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" "" "" { Text "D:\\quartus_20\\libraries\\megafunctions\\altpll.tdf" 290 2 0 } }  }  }
{  Info "ICUT_CUT_YGR_PLL_DETERMINED_TYPE" "Enhanced ddr_pll:inst\|altpll:altpll_component\|pll " "Chose type Enhanced for Auto type PLL ddr_pll:inst\|altpll:altpll_component\|pll" {  } {  }  }
{  Info "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO" "ddr_pll:inst\|altpll:altpll_component\|pll " "Can implement multiplication and division for ClockLock PLL ddr_pll:inst\|altpll:altpll_component\|pll" { { Info "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "5 1 0 0 ddr_pll:inst\|altpll:altpll_component\|_extclk0 " "Implementing clock multiplication of 5, clock division of 1, and phase shift of 0 degrees (0 ps) for ddr_pll:inst\|altpll:altpll_component\|_extclk0 port" {  } {  } } { Info "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "5 1 0 0 ddr_pll:inst\|altpll:altpll_component\|_extclk1 " "Implementing clock multiplication of 5, clock division of 1, and phase shift of 0 degrees (0 ps) for ddr_pll:inst\|altpll:altpll_component\|_extclk1 port" {  } {  } } { Info "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "5 1 0 0 ddr_pll:inst\|altpll:altpll_component\|_extclk2 " "Implementing clock multiplication of 5, clock division of 1, and phase shift of 0 degrees (0 ps) for ddr_pll:inst\|altpll:altpll_component\|_extclk2 port" {  } {  } } { Info "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "5 1 0 0 ddr_pll:inst\|altpll:altpll_component\|_extclk3 " "Implementing clock multiplication of 5, clock division of 1, and phase shift of 0 degrees (0 ps) for ddr_pll:inst\|altpll:altpll_component\|_extclk3 port" {  } {  } }  } {  }  }
{  Info "IMPP_MPP_ADVANCE_INFO" "EP1S10F780C7 " "Compilation Report contains advance information. Specifications for device EP1S10F780C7 are subject to change. Contact Altera for information on availability. No programming file will be generated." {  } {  }  }
{  Warning "WDAT_PRELIMINARY_TIMING" "EP1S10F780C7 " "Timing characteristics of device EP1S10F780C7 are preliminary" {  } {  }  }
{  Info "ITAN_SLACK_ANALYSIS" "" "Found complex timing assignments. Calculating slack delays instead of fmax." {  } {  }  }
{  Info "ITAN_NO_REG2REG_EXIST" "ddr_pll:inst\|altpll:altpll_component\|_extclk0 " "No valid register-to-register paths exist for clock ddr_pll:inst\|altpll:altpll_component\|_extclk0" {  } {  }  }
{  Info "ITAN_NO_REG2REG_EXIST" "ddr_pll:inst\|altpll:altpll_component\|_extclk1 " "No valid register-to-register paths exist for clock ddr_pll:inst\|altpll:altpll_component\|_extclk1" {  } {  }  }
{  Info "ITAN_NO_REG2REG_EXIST" "ddr_pll:inst\|altpll:altpll_component\|_extclk2 " "No valid register-to-register paths exist for clock ddr_pll:inst\|altpll:altpll_component\|_extclk2" {  } {  }  }
{  Info "ITAN_NO_REG2REG_EXIST" "ddr_pll:inst\|altpll:altpll_component\|_extclk3 " "No valid register-to-register paths exist for clock ddr_pll:inst\|altpll:altpll_component\|_extclk3" {  } {  }  }
{  Info "IDBC_ERROR_COUNT" "DDR_CLK Full compilation was successful 0 s 1  " "Design DDR_CLK: Full compilation was successful. 0 errors, 1 warning" {  } {  }  }