ddr_clk.eqn

vhdl编写的一个完整工程

--C1__locked is ddr_pll:inst|altpll:altpll_component|_locked at PLL_X27_Y31_N0
C1__locked = PLL.LOCKED(.FBIN(fbin), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(inclk0), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--C1__extclk0 is ddr_pll:inst|altpll:altpll_component|_extclk0 at PLL_X27_Y31_N0
C1__extclk0 = PLL.EXTCLK0(.FBIN(fbin), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(inclk0), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--C1__extclk1 is ddr_pll:inst|altpll:altpll_component|_extclk1 at PLL_X27_Y31_N0
C1__extclk1 = PLL.EXTCLK1(.FBIN(fbin), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(inclk0), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--C1__extclk2 is ddr_pll:inst|altpll:altpll_component|_extclk2 at PLL_X27_Y31_N0
C1__extclk2 = PLL.EXTCLK2(.FBIN(fbin), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(inclk0), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--C1__extclk3 is ddr_pll:inst|altpll:altpll_component|_extclk3 at PLL_X27_Y31_N0
C1__extclk3 = PLL.EXTCLK3(.FBIN(fbin), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(inclk0), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());


--fbin is fbin at Pin_H14
--operation mode is input

fbin = INPUT();


--inclk0 is inclk0 at Pin_K17
--operation mode is input

inclk0 = INPUT();


--locked is locked at Pin_J17
--operation mode is output

locked = OUTPUT(C1__locked);


--e0 is e0 at Pin_E15
--operation mode is output

e0 = OUTPUT(C1__extclk0);


--e[1] is e[1] at Pin_K14
--operation mode is output

e[1] = OUTPUT(C1__extclk1);


--e[2] is e[2] at Pin_C15
--operation mode is output

e[2] = OUTPUT(C1__extclk2);


--e[3] is e[3] at Pin_K16
--operation mode is output

e[3] = OUTPUT(C1__extclk3);


--A1L3 is e[1](n) at Pin_K15
--operation mode is output

A1L3 = LVDS_OUTPUT();


--A1L5 is e[2](n) at Pin_B15
--operation mode is output

A1L5 = LVDS_OUTPUT();


--A1L7 is e[3](n) at Pin_J16
--operation mode is output

A1L7 = LVDS_OUTPUT();