📄 ddr_clk.csf.rpt
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|AC27 |NC |
|AD28 |NC |
|AD27 |NC |
|AE28 |NC |
|AE27 |NC |
|AF28 |NC |
|AF27 |NC |
|C2 |NC |
|C1 |NC |
|D2 |NC |
|D1 |NC |
|E2 |NC |
|E1 |NC |
|F4 |NC |
|F3 |NC |
|F2 |NC |
|F1 |NC |
|G3 |NC |
|G4 |NC |
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|AB12 |NC |
|G12 |NC |
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|H20 |NC |
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|G21 |NC |
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|H9 |NC |
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|F9 |NC |
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|H10 |NC |
|AB9 |NC |
|AA10 |NC |
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|E3 |NC |
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|R10 |NC |
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|E11 |NC |
|E22 |NC |
+-----+-------------+-------------------+
+-----------------------------------------------------------------------------+
|Control Signals |
+-----------------------------------------------------------------------------+
+------+--------+-------+-----+------+--------------------+
|Name |Location|Fan-Out|Usage|Global|Global Resource Used|
+------+--------+-------+-----+------+--------------------+
|inclk0|K17 |1 |Clock|no |-- |
+------+--------+-------+-----+------+--------------------+
+-----------------------------------------------------------------------------+
|Non-Global High Fan-Out Signals |
+-----------------------------------------------------------------------------+
+----------------------------------------+-------+
|Name |Fan-Out|
+----------------------------------------+-------+
|ddr_pll:inst|altpll:altpll_component|pll|5 |
|inclk0 |1 |
|fbin |1 |
+----------------------------------------+-------+
+-----------------------------------------------------------------------------+
|PLL Summary |
+-----------------------------------------------------------------------------+
+----------------------------+----------------------------------------+
|PLL Property |ddr_pll:inst|altpll:altpll_component|pll|
+----------------------------+----------------------------------------+
|PLL type |Enhanced |
|Scan chain |None |
|PLL mode |External Feedback |
|Feedback source |extclock0 |
|Compensate clock |- |
|Switchover on loss of clock |Off |
|Switchover on gated lock |Off |
|Switchover counter |- |
|Primary clock |inclk0 |
|Input frequency 0 |33.33 MHz |
|Input frequency 1 |- |
|Nominal VCO frequency |333.33 MHz |
|Freq min lock |30.0 MHz |
|Freq max lock |100.0 MHz |
|Hold conf done |Off |
|M value |5 |
|N value |1 |
|M counter delay |0 ps |
|N counter delay |0 ps |
|M2 value |- |
|N2 value |- |
|SS counter |- |
|Downspread |- |
|Spread frequency |- |
|Charge pump current |50 uA |
|Loop filter resistance |1.02 KOhm |
|Loop filter capacitance |10 pF |
|Freq zero |1.51 MHz |
|Bandwidth |20 MHz |
|Freq pole |99.5 MHz |
|enable0 counter |- |
|enable1 counter |- |
|Real time reconfigurable |Off |
|Bit stream for reprogramming|- |
+----------------------------+----------------------------------------+
+-----------------------------------------------------------------------------+
|PLL Usage |
+-----------------------------------------------------------------------------+
+---------------------------------------------+------------+----+---+----------------+-----------+-----+----------+-------+-------------+-------------+----------+-------+-------+
|Name |Output Clock|Mult|Div|Output Frequency|Phase Shift|Delay|Duty Cycle|Counter|Counter Delay|Counter Value|High / Low|Initial|VCO Tap|
+---------------------------------------------+------------+----+---+----------------+-----------+-----+----------+-------+-------------+-------------+----------+-------+-------+
|ddr_pll:inst|altpll:altpll_component|_extclk0|extclock0 |5 |1 |166.67 MHz |0 (0 ps) |0 ps |50/50 |E0 |0 ps |2 |1/1 Even |1 |0 |
|ddr_pll:inst|altpll:altpll_component|_extclk1|extclock1 |5 |1 |166.67 MHz |0 (0 ps) |0 ps |50/50 |E1 |0 ps |2 |1/1 Even |1 |0 |
|ddr_pll:inst|altpll:altpll_component|_extclk2|extclock2 |5 |1 |166.67 MHz |0 (0 ps) |0 ps |50/50 |E2 |0 ps |2 |1/1 Even |1 |0 |
|ddr_pll:inst|altpll:altpll_component|_extclk3|extclock3 |5 |1 |166.67 MHz |0 (0 ps) |0 ps |50/50 |E3 |0 ps |2 |1/1 Even |1 |0 |
+---------------------------------------------+------------+----+---+----------------+-----------+-----+----------+-------+-------------+-------------+----------+-------+-------+
+-----------------------------------------------------------------------------+
|Interconnect Usage Summary |
+-----------------------------------------------------------------------------+
+---------------------------+------------------+
|Interconnect Resource Type |Usage |
+---------------------------+------------------+
|C16 interconnects |0 / 2,286 ( 0 % ) |
|C4 interconnects |0 / 31,320 ( 0 % )|
|C8 interconnects |0 / 7,272 ( 0 % ) |
|DIFFIOCLKs |0 / 16 ( 0 % ) |
|DQS I/O buses |0 / 16 ( 0 % ) |
|Direct links |0 / 44,710 ( 0 % )|
|Fast regional clocks |0 / 8 ( 0 % ) |
|Global clocks |0 / 16 ( 0 % ) |
|I/O buses |1 / 208 ( < 1 % ) |
|Local routing interconnects|0 / 10,570 ( 0 % )|
|R24 interconnects |0 / 2,280 ( 0 % ) |
|R4 interconnects |0 / 62,520 ( 0 % )|
|R8 interconnects |0 / 10,410 ( 0 % )|
|Regional clocks |0 / 16 ( 0 % ) |
+---------------------------+------------------+
+-----------------------------------------------------------------------------+
|Timing Settings |
+-----------------------------------------------------------------------------+
+---------------+-----------+----------------+----------------------------------------------------------------+------------------+
|Assignment File|Source Name|Destination Name|Option |Setting |
+---------------+-----------+----------------+----------------------------------------------------------------+------------------+
|DDR_CLK.psf |Include external delays to/from device pins in fmax calculations|Off |
|DDR_CLK.psf |Run All Timing Analyses |Off |
|DDR_CLK.psf |Ignore user-defined clock settings |Off |
|DDR_CLK.psf |Default hold multicycle |Same As Multicycle|
|DDR_CLK.psf |Cut off feedback from I/O pins |On |
|DDR_CLK.psf |Cut off clear and preset signal paths |On |
|DDR_CLK.psf |Cut off read during write signal paths |On |
|DDR_CLK.psf |Cut paths between unrelated clock domains |On |
|DDR_CLK.psf |Number of paths to report |200 |
|DDR_CLK.psf |Number of destination nodes to report |10 |
|DDR_CLK.psf |Number of source nodes to report per destination node |10 |
|DDR_CLK.psf |Maximum Strongly Connected Component loop size |50 |
|Device name |EP1S10F780C7 |
+---------------+-----------+----------------+----------------------------------------------------------------+------------------+
+-----------------------------------------------------------------------------+
|tco (Clock to Output Delays) |
+-----------------------------------------------------------------------------+
+---------------------------------------------------+------------+----------+
|Output Name |Required tco|Actual tco|
| -- Register Name | | |
| -- Clock Name | | |
+---------------------------------------------------+------------+----------+
|e0 |None |2.633 ns |
| -- ddr_pll:inst|altpll:altpll_component|_extclk0|None |2.633 ns |
| -- inclk0 |None |2.633 ns |
|e[1] |None |2.452 ns |
| -- ddr_pll:inst|altpll:altpll_component|_extclk1|None |2.452 ns |
| -- inclk0 |None |2.452 ns |
|e[2] |None |2.452 ns |
| -- ddr_pll:inst|altpll:altpll_component|_extclk2|None |2.452 ns |
| -- inclk0 |None |2.452 ns |
|e[3] |None |2.452 ns |
| -- ddr_pll:inst|altpll:altpll_component|_extclk3|None |2.452 ns |
| -- inclk0 |None |2.452 ns |
+---------------------------------------------------+------------+----------+
+-----------------------------------------------------------------------------+
|Processing Time |
+-----------------------------------------------------------------------------+
+-----------------+------------+
|Module Name |Elapsed Time|
+-----------------+------------+
|Database Builder |00:00:04 |
|Logic Synthesizer|00:00:01 |
|Fitter |00:00:48 |
|Assembler |00:00:00 |
|Delay Annotator |00:00:04 |
|Timing Analyzer |00:00:00 |
|Total |00:00:58 |
+-----------------+------------+
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