ddr_clk.csf.rpt

vhdl编写的一个完整工程

DDR_CLK - Quartus II Compilation Report File
-------------------------------------------------------------------------------

+-------------------------------------------------------------------------------------------------------------------------+
|Report Information                                                                                                       |
+------------------+------------------------------------------------------------------------------------------------------+
|Project           |D:\Data\Technical Marketing\Yeager\MFUG\examples\altpll\complete_project\ddr_clk\db\DDR_CLK.quartus_db|
|Compiler Settings |DDR_CLK                                                                                               |
|Quartus II Version|2.0 Build 204 03/26/2002 SP 1                                                                         |
+------------------+------------------------------------------------------------------------------------------------------+

Table of Contents
    Compilation Report
        Legal Notice
        Project Settings
            General Settings
        Results for "DDR_CLK" Compiler Settings
            Summary
            Compiler Settings
            Messages
            Hierarchy
            Post-Synthesis Resource Utilization by Entity
            Device Options
            Equations
            Floorplan View
            Pin-Out File
            Resource Section
                Resource Usage Summary
                Input Pins
                Output Pins
                All Package Pins
                Control Signals
                Non-Global High Fan-Out Signals
                PLL Summary
                PLL Usage
                LAB and Routing Section
                    Interconnect Usage Summary
            Timing Analyses
                Timing Settings
                tco (Clock to Output Delays)
            Processing Time

+-----------------------------------------------------------------------------+
|Legal Notice                                                                 |
+-----------------------------------------------------------------------------+
Copyright (C) 1991-2002 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.


+-----------------------------------------------------------------------------+
|General Settings                                                             |
+-----------------------------------------------------------------------------+
+-----------------+-------------------+
|Option           |Setting            |
+-----------------+-------------------+
|Start date & time|06/20/2002 08:50:49|
|Main task        |Compilation        |
|Settings name    |DDR_CLK            |
+-----------------+-------------------+

+-----------------------------------------------------------------------------+
|Summary                                                                      |
+-----------------------------------------------------------------------------+
+-----------------------------------+---------------------------------------------+
|Processing status                  |Fitting Successful - Thu Jun 20 08:52:02 2002|
|Timing requirements/analysis status|No requirements                              |
|Chip name                          |DDR_CLK                                      |
|Device name                        |EP1S10F780C7                                 |
|Total logic elements               |0 / 10,570 ( 0 % )                           |
|Total pins                         |10 / 426 ( 2 % )                             |
|Total memory bits                  |0 / 920,448 ( 0 % )                          |
|DSP block 9-bit elements           |0 / 48 ( 0 % )                               |
+-----------------------------------+---------------------------------------------+

+-----------------------------------------------------------------------------+
|Compiler Settings                                                            |
+-----------------------------------------------------------------------------+
+------------------------------------------+------------------+
|Option                                    |Setting           |
+------------------------------------------+------------------+
|Chip name                                 |DDR_CLK           |
|Family name                               |Stratix           |
|Focus entity name                         ||DDR_CLK          |
|Device                                    |EP1S10F780C7      |
|Compilation mode                          |Full              |
|Disk space/compilation speed tradeoff     |Normal            |
|Preserve fewer node names                 |On                |
|Optimize timing                           |Normal Compilation|
|Optimize IOC register placement for timing|On                |
|Generate timing analyses                  |On                |
|Fast Fit compilation                      |Off               |
|SignalProbe compilation                   |Off               |
+------------------------------------------+------------------+

+-----------------------------------------------------------------------------+
|Messages                                                                     |
+-----------------------------------------------------------------------------+
Info: Found 1 design units and 1 entities in source file D:\Data\Technical Marketing\Yeager\MFUG\examples\altpll\complete_project\ddr_clk\DDR_CLK.bdf
  Info: Found entity 1: DDR_CLK
Info: Found 0 design units and 0 entities in source file D:\Data\Technical Marketing\Yeager\MFUG\examples\altpll\complete_project\ddr_clk\DDR_CLK.vwf
Info: Found 1 design units and 1 entities in source file D:\Data\Technical Marketing\Yeager\MFUG\examples\altpll\complete_project\ddr_clk\ddr_pll.tdf
  Info: Found entity 1: ddr_pll
Info: Found 1 design units and 1 entities in source file D:\quartus_20\libraries\megafunctions\altpll.tdf
  Info: Found entity 1: altpll
Info: Implemented 8 device resources
  Info: Implemented 2 input pins
  Info: Implemented 5 output pins
  Info: Implemented 1 ClockLock PLLs
Info: Selected device EP1S10F780C7 for design DDR_CLK
Info: Compensating output pin e0, which is fed by extclk0 port of enhanced PLL ddr_pll:inst|altpll:altpll_component|pll
Info: Chose type Enhanced for Auto type PLL ddr_pll:inst|altpll:altpll_component|pll
Info: Can implement multiplication and division for ClockLock PLL ddr_pll:inst|altpll:altpll_component|pll
  Info: Implementing clock multiplication of 5, clock division of 1, and phase shift of 0 degrees (0 ps) for ddr_pll:inst|altpll:altpll_component|_extclk0 port
  Info: Implementing clock multiplication of 5, clock division of 1, and phase shift of 0 degrees (0 ps) for ddr_pll:inst|altpll:altpll_component|_extclk1 port
  Info: Implementing clock multiplication of 5, clock division of 1, and phase shift of 0 degrees (0 ps) for ddr_pll:inst|altpll:altpll_component|_extclk2 port
  Info: Implementing clock multiplication of 5, clock division of 1, and phase shift of 0 degrees (0 ps) for ddr_pll:inst|altpll:altpll_component|_extclk3 port
Info: Compilation Report contains advance information. Specifications for device EP1S10F780C7 are subject to change. Contact Altera for information on availability. No programming file will be generated.
Warning: Timing characteristics of device EP1S10F780C7 are preliminary
Info: Found complex timing assignments. Calculating slack delays instead of fmax.
Info: No valid register-to-register paths exist for clock ddr_pll:inst|altpll:altpll_component|_extclk0
Info: No valid register-to-register paths exist for clock ddr_pll:inst|altpll:altpll_component|_extclk1
Info: No valid register-to-register paths exist for clock ddr_pll:inst|altpll:altpll_component|_extclk2
Info: No valid register-to-register paths exist for clock ddr_pll:inst|altpll:altpll_component|_extclk3
Info: Design DDR_CLK: Full compilation was successful. 0 errors, 1 warning

+-----------------------------------------------------------------------------+
|Hierarchy                                                                    |
+-----------------------------------------------------------------------------+
CompileHierarchy
  DDR_CLK
    ddr_pll:inst
      altpll:altpll_component

+-----------------------------------------------------------------------------+
|Post-Synthesis Resource Utilization by Entity                                |
+-----------------------------------------------------------------------------+
+-------------------------------+-----------+---------+---------------+------------+----+---------------------------------------------+
|Compilation Hierarchy Node     |Logic Cells|Registers|Memory Segments|DSP Elements|Pins|Full Hierarchy Name                          |
+-------------------------------+-----------+---------+---------------+------------+----+---------------------------------------------+
||DDR_CLK                       |0          |0        |0              |0           |7   ||DDR_CLK                                     |
|   |ddr_pll:inst|              |0          |0        |0              |0           |0   ||DDR_CLK|ddr_pll:inst                        |
|      |altpll:altpll_component||0          |0        |0              |0           |0   ||DDR_CLK|ddr_pll:inst|altpll:altpll_component|
+-------------------------------+-----------+---------+---------------+------------+----+---------------------------------------------+

+-----------------------------------------------------------------------------+
|Device Options                                                               |
+-----------------------------------------------------------------------------+
+----------------------------------------------------------------+------------------------+
|Option                                                          |Setting                 |
+----------------------------------------------------------------+------------------------+
|Auto-restart configuration after error                          |Off                     |
|Release clears before tri-states                                |Off                     |
|Enable user-supplied start-up clock (CLKUSR)                    |Off                     |
|Enable device-wide reset (DEV_CLRn)                             |Off                     |
|Enable device-wide output enable (DEV_OE)                       |Off                     |
|Enable INIT_DONE output                                         |Off                     |
|Auto-increment JTAG user code for multiple configuration devices|On                      |
|Disable CONF_DONE and nSTATUS pull-ups on configuration device  |Off                     |
|Generate Tabular Text File (.ttf)                               |Off                     |
|Generate Raw Binary File (.rbf)                                 |Off                     |
|Generate Hexadecimal Output File (.hexout)                      |Off                     |
|Configuration scheme                                            |Passive Serial          |
|Hexadecimal Output File count direction                         |Up                      |
|JTAG user code for target device                                |0XFFFFFFFF              |
|JTAG user code for configuration device                         |0XFFFFFFFF              |
|Hexadecimal Output File start address                           |0                       |
|Reserve all unused pins                                         |As output driving ground|
|Configuration device                                            |EPC2                    |
|Use check sum as user code                                      |Off                     |
|Use check sum as user code for EPROM                            |Off                     |
+----------------------------------------------------------------+------------------------+

+-----------------------------------------------------------------------------+
|Equations                                                                    |
+-----------------------------------------------------------------------------+
The equations can be found in D:\Data\Technical Marketing\Yeager\MFUG\examples\altpll\complete_project\ddr_clk\DDR_CLK.eqn.

+-----------------------------------------------------------------------------+
|Floorplan View                                                               |
+-----------------------------------------------------------------------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.

+-----------------------------------------------------------------------------+
|Pin-Out File                                                                 |
+-----------------------------------------------------------------------------+
The pin-out file can be found in D:\Data\Technical Marketing\Yeager\MFUG\examples\altpll\complete_project\ddr_clk\DDR_CLK.pin.

+-----------------------------------------------------------------------------+
|Resource Usage Summary                                                       |
+-----------------------------------------------------------------------------+
+------------------------+----------------------------------------+
|Resource                |Usage                                   |
+------------------------+----------------------------------------+
|Logic cells             |0 / 10,570 ( 0 % )                      |
|Flipflops               |0 / 11,848 ( 0 % )                      |
|I/O pins                |10 / 426 ( 2 % )                        |
|Clock pins              |1                                       |
|Dedicated input pins    |0                                       |
|Global signals          |0                                       |
|M512s                   |0 / 94 ( 0 % )                          |
|M4Ks                    |0 / 60 ( 0 % )                          |
|MegaRAMs                |0 / 1 ( 0 % )                           |
|Total memory bits       |0 / 920,448 ( 0 % )                     |
|DSP block 9-bit elements|0 / 48 ( 0 % )                          |
|PLLs                    |1 / 6 ( 16 % )                          |
|Global clocks           |0 / 16 ( 0 % )                          |
|Regional clocks         |0 / 16 ( 0 % )                          |
|Fast regional clocks    |0 / 8 ( 0 % )                           |
|DIFFIOCLKs              |0 / 16 ( 0 % )                          |
|SERDES transmitters     |0 / 44 ( 0 % )                          |
|SERDES receivers        |0 / 44 ( 0 % )                          |
|Maximum fan-out node    |ddr_pll:inst|altpll:altpll_component|pll|
|Maximum fan-out         |5                                       |
|Total fan-out           |7                                       |
|Average fan-out         |0.64                                    |
+------------------------+----------------------------------------+

+-----------------------------------------------------------------------------+
|Input Pins                                                                   |
+-----------------------------------------------------------------------------+
+------+-----+------------+------------+-----------+---------------------+------------------+------+--------------+-------------+--------------+-----------+---------------+--------+------------+---------+--------------+--------------------------+
|Name  |Pin #|X coordinate|Y coordinate|Cell number|Combinational Fan-Out|Registered Fan-Out|Global|Input Register|Power Up High|Slow Slew Rate|Delay Chain|PCI I/O Enabled|Bus Hold|Weak Pull Up|Turbo Bit|I/O Standard  |OCT and Impedance Matching|
+------+-----+------------+------------+-----------+---------------------+------------------+------+--------------+-------------+--------------+-----------+---------------+--------+------------+---------+--------------+--------------------------+
|fbin  |H14  |25          |31          |0          |1                    |0                 |no    |no            |no           |no            |no         |no             |no      |Off         |no       |SSTL-2 Class I|Off                       |
|inclk0|K17  |21          |31          |2          |1                    |0                 |no    |no            |no           |no            |no         |no             |no      |Off         |no       |LVTTL         |Off                       |
+------+-----+------------+------------+-----------+---------------------+------------------+------+--------------+-------------+--------------+-----------+---------------+--------+------------+---------+--------------+--------------------------+

+-----------------------------------------------------------------------------+
|Output Pins                                                                  |
+-----------------------------------------------------------------------------+
+-------+-----+------------+------------+-----------+---------------+----------------------+-------------+--------------+---------------+---------------+----------+--------+------------+---------+-------------------+----------------+--------------------------+
|Name   |Pin #|X coordinate|Y coordinate|Cell number|Output Register|Output Enable Register|Power Up High|Slow Slew Rate|TCO Delay Chain|PCI I/O Enabled|Open Drain|Bus Hold|Weak Pull Up|Turbo Bit|I/O Standard       |Current Strength|OCT and Impedance Matching|
+-------+-----+------------+------------+-----------+---------------+----------------------+-------------+--------------+---------------+---------------+----------+--------+------------+---------+-------------------+----------------+--------------------------+
|e0     |E15  |25          |31          |4          |no             |no                    |no           |no            |no             |no             |no        |no      |Off         |no       |SSTL-2 Class I     |Minimum Current |Off                       |
|e[1]   |K14  |25          |31          |2          |no             |no                    |no           |no            |no             |no             |no        |no      |Off         |no       |Differential SSTL-2|Minimum Current |Off                       |
|e[1](n)|K15  |25          |31          |3          |no             |no                    |no           |no            |no             |no             |no        |no      |Off         |no       |Differential SSTL-2|Minimum Current |Off                       |
|e[2]   |C15  |23          |31          |4          |no             |no                    |no           |no            |no             |no             |no        |no      |Off         |no       |Differential SSTL-2|Minimum Current |Off                       |
|e[2](n)|B15  |23          |31          |5          |no             |no                    |no           |no            |no             |no             |no        |no      |Off         |no       |Differential SSTL-2|Minimum Current |Off                       |
|e[3]   |K16  |23          |31          |2          |no             |no                    |no           |no            |no             |no             |no        |no      |Off         |no       |Differential SSTL-2|Minimum Current |Off                       |
|e[3](n)|J16  |23          |31          |3          |no             |no                    |no           |no            |no             |no             |no        |no      |Off         |no       |Differential SSTL-2|Minimum Current |Off                       |
|locked |J17  |21          |31          |3          |no             |no                    |no           |no            |no             |no             |no        |no      |Off         |no       |LVTTL              |24mA            |Off                       |
+-------+-----+------------+------------+-----------+---------------+----------------------+-------------+--------------+---------------+---------------+----------+--------+------------+---------+-------------------+----------------+--------------------------+

+-----------------------------------------------------------------------------+
|All Package Pins                                                             |
+-----------------------------------------------------------------------------+
+-----+-------------+-------------------+
|Pin #|Usage        |I/O Standard       |
+-----+-------------+-------------------+
|G27  |GND*         |
|G28  |GND*         |
|K21  |GND*         |
|K22  |GND*         |
|H26  |GND*         |
|H25  |GND*         |
|L22  |GND*         |
|L21  |GND*         |
|H27  |GND*         |
|H28  |GND*         |
|L23  |GND*         |
|L24  |GND*         |
|E24  |GND          |
|J25  |GND*         |
|J26  |GND*         |
|L20  |GND*         |
|L19  |GND*         |
|J27  |GND*         |
|J28  |GND*         |
|M22  |GND*         |
|M21  |GND*         |
|K26  |GND*         |
|K25  |GND*         |
|M24  |GND*         |
|M23  |GND*         |
|K27  |GND*         |
|K28  |GND*         |
|M20  |GND*         |
|M19  |GND*         |
|L25  |GND*         |
|L26  |GND*         |
|N26  |GND*         |
|N25  |GND*         |
|L27  |GND*         |