uart.hier_info

来自「quatus II 环境下vhdl实现RS232功能」· HIER_INFO 代码 · 共 318 行

|uart_test
rxd_readyH <= uart:inst.rxd_readyH
clk => uart:inst.clk
clk => scan:inst6.clk
clk => clk_div:inst1.clk_in
rst_n => uart:inst.rst_n
rst_n => scan:inst6.rst
rxd => uart:inst.rxd
txd_startH => uart:inst.txd_startH
sel[0] => uart:inst.sel[0]
sel[1] => uart:inst.sel[1]
sel[2] => uart:inst.sel[2]
txd_doneH <= uart:inst.txd_doneH
txd <= uart:inst.txd
dig4 <= scan:inst6.com_mten
dig3 <= scan:inst6.com_mone
dig2 <= scan:inst6.com_sten
dig1 <= scan:inst6.com_sone
seven_seg[0] <= scan:inst6.seven_seg[0]
seven_seg[1] <= scan:inst6.seven_seg[1]
seven_seg[2] <= scan:inst6.seven_seg[2]
seven_seg[3] <= scan:inst6.seven_seg[3]
seven_seg[4] <= scan:inst6.seven_seg[4]
seven_seg[5] <= scan:inst6.seven_seg[5]
seven_seg[6] <= scan:inst6.seven_seg[6]
seven_seg[7] <= scan:inst6.seven_seg[7]


|uart_test|uart:inst
rxd_readyH <= uart_receiver:inst.rxd_readyH
clk => uart_receiver:inst.sysclk
clk => br_gen:inst2.sysclk
clk => uart_transmitter:inst1.sysclk
rst_n => uart_receiver:inst.rst_n
rst_n => uart_transmitter:inst1.rst_n
sel[0] => br_gen:inst2.sel[0]
sel[1] => br_gen:inst2.sel[1]
sel[2] => br_gen:inst2.sel[2]
rxd => uart_receiver:inst.rxd
txd <= uart_transmitter:inst1.txd
txd_startH => uart_transmitter:inst1.txd_startH
DBUS[0] => uart_transmitter:inst1.DBUS[0]
DBUS[1] => uart_transmitter:inst1.DBUS[1]
DBUS[2] => uart_transmitter:inst1.DBUS[2]
DBUS[3] => uart_transmitter:inst1.DBUS[3]
DBUS[4] => uart_transmitter:inst1.DBUS[4]
DBUS[5] => uart_transmitter:inst1.DBUS[5]
DBUS[6] => uart_transmitter:inst1.DBUS[6]
DBUS[7] => uart_transmitter:inst1.DBUS[7]
txd_doneH <= uart_transmitter:inst1.txd_doneH
rxd_data[0] <= uart_receiver:inst.RDR[0]
rxd_data[1] <= uart_receiver:inst.RDR[1]
rxd_data[2] <= uart_receiver:inst.RDR[2]
rxd_data[3] <= uart_receiver:inst.RDR[3]
rxd_data[4] <= uart_receiver:inst.RDR[4]
rxd_data[5] <= uart_receiver:inst.RDR[5]
rxd_data[6] <= uart_receiver:inst.RDR[6]
rxd_data[7] <= uart_receiver:inst.RDR[7]


|uart_test|uart:inst|uart_receiver:inst
sysclk => rxd_readyH~reg0.CLK
sysclk => RSR[0].CLK
sysclk => RSR[1].CLK
sysclk => RSR[2].CLK
sysclk => RSR[3].CLK
sysclk => RSR[4].CLK
sysclk => RSR[5].CLK
sysclk => RSR[6].CLK
sysclk => RSR[7].CLK
sysclk => RDR[0]~reg0.CLK
sysclk => RDR[1]~reg0.CLK
sysclk => RDR[2]~reg0.CLK
sysclk => RDR[3]~reg0.CLK
sysclk => RDR[4]~reg0.CLK
sysclk => RDR[5]~reg0.CLK
sysclk => RDR[6]~reg0.CLK
sysclk => RDR[7]~reg0.CLK
sysclk => ct2[0].CLK
sysclk => ct2[1].CLK
sysclk => ct2[2].CLK
sysclk => ct2[3].CLK
sysclk => ct1[0].CLK
sysclk => ct1[1].CLK
sysclk => ct1[2].CLK
sysclk => bclkx8_dlayed.CLK
sysclk => state~0.IN1
rst_n => RDR[0]~reg0.PRESET
rst_n => RDR[1]~reg0.PRESET
rst_n => RDR[2]~reg0.ACLR
rst_n => RDR[3]~reg0.PRESET
rst_n => RDR[4]~reg0.ACLR
rst_n => RDR[5]~reg0.PRESET
rst_n => RDR[6]~reg0.ACLR
rst_n => RDR[7]~reg0.ACLR
rst_n => ct2[0].ACLR
rst_n => ct2[1].ACLR
rst_n => ct2[2].ACLR
rst_n => ct2[3].ACLR
rst_n => ct1[0].ACLR
rst_n => ct1[1].ACLR
rst_n => ct1[2].ACLR
rst_n => bclkx8_dlayed.ACLR
rst_n => rxd_readyH~reg0.ENA
rst_n => state~1.IN1
bclkx8 => bclkx8_rising.IN1
bclkx8 => bclkx8_dlayed.DATAIN
rxd => Selector0.IN2
rxd => nextstate~1.DATAA
rxd => nextstate~0.OUTPUTSELECT
rxd => clr1~0.OUTPUTSELECT
rxd => inc1~0.OUTPUTSELECT
rxd => ok_en~0.DATAA
rxd => Selector1.IN1
rxd => RSR[7].DATAIN
rxd_readyH <= rxd_readyH~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDR[0] <= RDR[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDR[1] <= RDR[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDR[2] <= RDR[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDR[3] <= RDR[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDR[4] <= RDR[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDR[5] <= RDR[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDR[6] <= RDR[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RDR[7] <= RDR[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|uart_test|uart:inst|br_gen:inst2
sysclk => cnt2.CLK
sysclk => cnt1[0].CLK
sysclk => cnt1[1].CLK
sysclk => cnt1[2].CLK
sysclk => cnt1[3].CLK
sysclk => cnt1[4].CLK
sel[0] => Mux0.IN2
sel[1] => Mux0.IN1
sel[2] => Mux0.IN0
bclkx8 <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
bclk <= ctr3[2].DB_MAX_OUTPUT_PORT_TYPE


|uart_test|uart:inst|uart_transmitter:inst1
sysclk => txd_startH_d1.CLK
sysclk => txd_startH_d0.CLK
sysclk => bclk_dlayed.CLK
sysclk => bct[0].CLK
sysclk => bct[1].CLK
sysclk => bct[2].CLK
sysclk => bct[3].CLK
sysclk => tsr[0].CLK
sysclk => tsr[1].CLK
sysclk => tsr[2].CLK
sysclk => tsr[3].CLK
sysclk => tsr[4].CLK
sysclk => tsr[5].CLK
sysclk => tsr[6].CLK
sysclk => tsr[7].CLK
sysclk => tsr[8].CLK
sysclk => state~0.IN1
rst_n => bclk_dlayed.ACLR
rst_n => bct[0].ACLR
rst_n => bct[1].ACLR
rst_n => bct[2].ACLR
rst_n => bct[3].ACLR
rst_n => tsr[0].PRESET
rst_n => tsr[1].PRESET
rst_n => tsr[2].PRESET
rst_n => tsr[3].PRESET
rst_n => tsr[4].PRESET
rst_n => tsr[5].PRESET
rst_n => tsr[6].PRESET
rst_n => tsr[7].PRESET
rst_n => tsr[8].PRESET
rst_n => txd_startH_d0.ENA
rst_n => txd_startH_d1.ENA
rst_n => state~1.IN1
bclk => bclk_rising.IN1
bclk => bclk_dlayed.DATAIN
txd_startH => txd_startH_d0.DATAIN
DBUS[0] => tsr~25.DATAB
DBUS[1] => tsr~24.DATAB
DBUS[2] => tsr~23.DATAB
DBUS[3] => tsr~22.DATAB
DBUS[4] => tsr~21.DATAB
DBUS[5] => tsr~20.DATAB
DBUS[6] => tsr~19.DATAB
DBUS[7] => tsr~18.DATAB
txd_doneH <= txd_done~1.DB_MAX_OUTPUT_PORT_TYPE
txd <= tsr[0].DB_MAX_OUTPUT_PORT_TYPE


|uart_test|scan:inst6
clk => min_ten[0].CLK
clk => min_ten[1].CLK
clk => min_ten[2].CLK
clk => min_ten[3].CLK
clk => min_one[0].CLK
clk => min_one[1].CLK
clk => min_one[2].CLK
clk => min_one[3].CLK
clk => sec_ten[0].CLK
clk => sec_ten[1].CLK
clk => sec_ten[2].CLK
clk => sec_ten[3].CLK
clk => sec_one[0].CLK
clk => sec_one[1].CLK
clk => sec_one[2].CLK
clk => sec_one[3].CLK
clk_scan => bin[0].CLK
clk_scan => bin[1].CLK
clk_scan => bin[2].CLK
clk_scan => bin[3].CLK
clk_scan => sel[0].CLK
clk_scan => sel[1].CLK
clk_scan => com_mone~reg0.CLK
clk_scan => com_mten~reg0.CLK
clk_scan => com_sone~reg0.CLK
clk_scan => com_sten~reg0.CLK
rst => com_sten~reg0.ACLR
rst => com_sone~reg0.ACLR
rst => com_mten~reg0.ACLR
rst => com_mone~reg0.ACLR
rst => sel[1].ACLR
rst => sel[0].ACLR
rst => min_ten[0].ACLR
rst => min_ten[1].ACLR
rst => min_ten[2].ACLR
rst => min_ten[3].ACLR
rst => min_one[0].ACLR
rst => min_one[1].ACLR
rst => min_one[2].ACLR
rst => min_one[3].ACLR
rst => sec_ten[0].ALOAD
rst => sec_ten[1].ALOAD
rst => sec_ten[2].ALOAD
rst => sec_ten[3].ALOAD
rst => sec_one[0].ALOAD
rst => sec_one[1].ALOAD
rst => sec_one[2].ALOAD
rst => sec_one[3].ALOAD
rst => bin[0].ENA
rst => bin[1].ENA
rst => bin[2].ENA
rst => bin[3].ENA
rxd_readyH => min_ten[0].ENA
rxd_readyH => min_ten[1].ENA
rxd_readyH => min_ten[2].ENA
rxd_readyH => min_ten[3].ENA
rxd_readyH => min_one[0].ENA
rxd_readyH => min_one[1].ENA
rxd_readyH => min_one[2].ENA
rxd_readyH => min_one[3].ENA
rxd_readyH => sec_ten[0].ENA
rxd_readyH => sec_ten[1].ENA
rxd_readyH => sec_ten[2].ENA
rxd_readyH => sec_ten[3].ENA
rxd_readyH => sec_one[0].ENA
rxd_readyH => sec_one[1].ENA
rxd_readyH => sec_one[2].ENA
rxd_readyH => sec_one[3].ENA
rxd_data[0] => sec_one[0].ADATA
rxd_data[0] => sec_one[0].DATAIN
rxd_data[1] => sec_one[1].ADATA
rxd_data[1] => sec_one[1].DATAIN
rxd_data[2] => sec_one[2].ADATA
rxd_data[2] => sec_one[2].DATAIN
rxd_data[3] => sec_one[3].ADATA
rxd_data[3] => sec_one[3].DATAIN
rxd_data[4] => sec_ten[0].ADATA
rxd_data[4] => sec_ten[0].DATAIN
rxd_data[5] => sec_ten[1].ADATA
rxd_data[5] => sec_ten[1].DATAIN
rxd_data[6] => sec_ten[2].ADATA
rxd_data[6] => sec_ten[2].DATAIN
rxd_data[7] => sec_ten[3].ADATA
rxd_data[7] => sec_ten[3].DATAIN
seven_seg[0] <= Mux14.DB_MAX_OUTPUT_PORT_TYPE
seven_seg[1] <= Mux13.DB_MAX_OUTPUT_PORT_TYPE
seven_seg[2] <= Mux12.DB_MAX_OUTPUT_PORT_TYPE
seven_seg[3] <= Mux11.DB_MAX_OUTPUT_PORT_TYPE
seven_seg[4] <= Mux10.DB_MAX_OUTPUT_PORT_TYPE
seven_seg[5] <= Mux9.DB_MAX_OUTPUT_PORT_TYPE
seven_seg[6] <= Mux8.DB_MAX_OUTPUT_PORT_TYPE
seven_seg[7] <= <GND>
com_mten <= com_mten~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_mone <= com_mone~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_sten <= com_sten~reg0.DB_MAX_OUTPUT_PORT_TYPE
com_sone <= com_sone~reg0.DB_MAX_OUTPUT_PORT_TYPE


|uart_test|clk_div:inst1
clk_in => cnt[0].CLK
clk_in => cnt[1].CLK
clk_in => cnt[2].CLK
clk_in => cnt[3].CLK
clk_in => cnt[4].CLK
clk_in => cnt[5].CLK
clk_in => cnt[6].CLK
clk_in => cnt[7].CLK
clk_in => cnt[8].CLK
clk_in => cnt[9].CLK
clk_in => cnt[10].CLK
clk_in => cnt[11].CLK
clk_in => cnt[12].CLK
clk_in => cnt[13].CLK
clk_in => cnt[14].CLK
clk_in => cnt[15].CLK
clk_in => cnt[16].CLK
clk_in => cnt[17].CLK
clk_in => cnt[18].CLK
clk_in => cnt[19].CLK
clk_in => cnt[20].CLK
clk_in => cnt[21].CLK
clk_in => cnt[22].CLK
clk_in => cnt[23].CLK
clk_out1 <= cnt[13].DB_MAX_OUTPUT_PORT_TYPE