uart.map.qmsg

来自「quatus II 环境下vhdl实现RS232功能」· QMSG 代码 · 共 33 行 · 第 1/2 页

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scan scan:inst6 " "Info: Elaborating entity \"scan\" for hierarchy \"scan:inst6\"" {  } { { "uart_test.bdf" "inst6" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_test.bdf" { { 360 296 496 488 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "rxd_data scan.vhd(26) " "Warning (10492): VHDL Process Statement warning at scan.vhd(26): signal \"rxd_data\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "scan.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/scan.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "rxd_data scan.vhd(27) " "Warning (10492): VHDL Process Statement warning at scan.vhd(27): signal \"rxd_data\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "scan.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/scan.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_div clk_div:inst1 " "Info: Elaborating entity \"clk_div\" for hierarchy \"clk_div:inst1\"" {  } { { "uart_test.bdf" "inst1" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_test.bdf" { { 280 336 456 344 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset clk_div.vhd(18) " "Warning (10492): VHDL Process Statement warning at clk_div.vhd(18): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "clk_div.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/clk_div.vhd" 18 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|uart_test\|uart:inst\|uart_transmitter:inst1\|state 3 " "Info: State machine \"\|uart_test\|uart:inst\|uart_transmitter:inst1\|state\" contains 3 states" {  } { { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 18 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|uart_test\|uart:inst\|uart_receiver:inst\|state 3 " "Info: State machine \"\|uart_test\|uart:inst\|uart_receiver:inst\|state\" contains 3 states" {  } { { "uart_receiver.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_receiver.vhd" 19 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|uart_test\|uart:inst\|uart_transmitter:inst1\|state " "Info: Selected Auto state machine encoding method for state machine \"\|uart_test\|uart:inst\|uart_transmitter:inst1\|state\"" {  } { { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 18 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|uart_test\|uart:inst\|uart_transmitter:inst1\|state " "Info: Encoding result for state machine \"\|uart_test\|uart:inst\|uart_transmitter:inst1\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart:inst\|uart_transmitter:inst1\|state.tdata " "Info: Encoded state bit \"uart:inst\|uart_transmitter:inst1\|state.tdata\"" {  } { { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart:inst\|uart_transmitter:inst1\|state.synch " "Info: Encoded state bit \"uart:inst\|uart_transmitter:inst1\|state.synch\"" {  } { { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart:inst\|uart_transmitter:inst1\|state.idle " "Info: Encoded state bit \"uart:inst\|uart_transmitter:inst1\|state.idle\"" {  } { { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_test\|uart:inst\|uart_transmitter:inst1\|state.idle 000 " "Info: State \"\|uart_test\|uart:inst\|uart_transmitter:inst1\|state.idle\" uses code string \"000\"" {  } { { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_test\|uart:inst\|uart_transmitter:inst1\|state.synch 011 " "Info: State \"\|uart_test\|uart:inst\|uart_transmitter:inst1\|state.synch\" uses code string \"011\"" {  } { { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_test\|uart:inst\|uart_transmitter:inst1\|state.tdata 101 " "Info: State \"\|uart_test\|uart:inst\|uart_transmitter:inst1\|state.tdata\" uses code string \"101\"" {  } { { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 18 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|uart_test\|uart:inst\|uart_receiver:inst\|state " "Info: Selected Auto state machine encoding method for state machine \"\|uart_test\|uart:inst\|uart_receiver:inst\|state\"" {  } { { "uart_receiver.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_receiver.vhd" 19 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|uart_test\|uart:inst\|uart_receiver:inst\|state " "Info: Encoding result for state machine \"\|uart_test\|uart:inst\|uart_receiver:inst\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart:inst\|uart_receiver:inst\|state.recv_data " "Info: Encoded state bit \"uart:inst\|uart_receiver:inst\|state.recv_data\"" {  } { { "uart_receiver.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_receiver.vhd" 81 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart:inst\|uart_receiver:inst\|state.start_detected " "Info: Encoded state bit \"uart:inst\|uart_receiver:inst\|state.start_detected\"" {  } { { "uart_receiver.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_receiver.vhd" 81 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "uart:inst\|uart_receiver:inst\|state.idle " "Info: Encoded state bit \"uart:inst\|uart_receiver:inst\|state.idle\"" {  } { { "uart_receiver.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_receiver.vhd" 81 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_test\|uart:inst\|uart_receiver:inst\|state.idle 000 " "Info: State \"\|uart_test\|uart:inst\|uart_receiver:inst\|state.idle\" uses code string \"000\"" {  } { { "uart_receiver.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_receiver.vhd" 81 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_test\|uart:inst\|uart_receiver:inst\|state.start_detected 011 " "Info: State \"\|uart_test\|uart:inst\|uart_receiver:inst\|state.start_detected\" uses code string \"011\"" {  } { { "uart_receiver.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_receiver.vhd" 81 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_test\|uart:inst\|uart_receiver:inst\|state.recv_data 101 " "Info: State \"\|uart_test\|uart:inst\|uart_receiver:inst\|state.recv_data\" uses code string \"101\"" {  } { { "uart_receiver.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_receiver.vhd" 81 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "uart_receiver.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_receiver.vhd" 19 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "seven_seg\[7\] GND " "Warning: Pin \"seven_seg\[7\]\" stuck at GND" {  } { { "uart_test.bdf" "" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_test.bdf" { { 384 520 717 400 "seven_seg\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } } { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } } { "uart_receiver.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_receiver.vhd" 81 -1 0 } } { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } } { "uart_receiver.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_receiver.vhd" 81 -1 0 } } { "uart_receiver.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_receiver.vhd" 81 -1 0 } } { "uart_receiver.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_receiver.vhd" 81 -1 0 } } { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } } { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } } { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } } { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } } { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } } { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "204 " "Info: Implemented 204 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "182 " "Info: Implemented 182 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 07 10:42:22 2008 " "Info: Processing ended: Mon Jan 07 10:42:22 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}