uart.map.qmsg

来自「quatus II 环境下vhdl实现RS232功能」· QMSG 代码 · 共 33 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 07 10:42:19 2008 " "Info: Processing started: Mon Jan 07 10:42:19 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uart -c uart " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart -c uart" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "br_gen.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file br_gen.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 br_gen-arch " "Info: Found design unit 1: br_gen-arch" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 br_gen " "Info: Found entity 1: br_gen" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart.vhd " "Warning: Can't analyze file -- file F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_receiver.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file uart_receiver.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 uart_receiver-arch " "Info: Found design unit 1: uart_receiver-arch" {  } { { "uart_receiver.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_receiver.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 uart_receiver " "Info: Found entity 1: uart_receiver" {  } { { "uart_receiver.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_receiver.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_transmitter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file uart_transmitter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 uart_transmitter-arch " "Info: Found design unit 1: uart_transmitter-arch" {  } { { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 uart_transmitter " "Info: Found entity 1: uart_transmitter" {  } { { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file uart_test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 uart_test " "Info: Found entity 1: uart_test" {  } { { "uart_test.bdf" "" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_div.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clk_div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clk_div-a " "Info: Found design unit 1: clk_div-a" {  } { { "clk_div.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/clk_div.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clk_div " "Info: Found entity 1: clk_div" {  } { { "clk_div.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/clk_div.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "scan.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file scan.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 scan-arch " "Info: Found design unit 1: scan-arch" {  } { { "scan.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/scan.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 scan " "Info: Found entity 1: scan" {  } { { "scan.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/scan.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/Block1.bdf " "Warning: Can't analyze file -- file F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/Block1.bdf is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file uart.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 uart " "Info: Found entity 1: uart" {  } { { "uart.bdf" "" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "uart_test " "Info: Elaborating entity \"uart_test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart uart:inst " "Info: Elaborating entity \"uart\" for hierarchy \"uart:inst\"" {  } { { "uart_test.bdf" "inst" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_test.bdf" { { 112 288 496 256 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_receiver uart:inst\|uart_receiver:inst " "Info: Elaborating entity \"uart_receiver\" for hierarchy \"uart:inst\|uart_receiver:inst\"" {  } { { "uart.bdf" "inst" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart.bdf" { { 160 312 456 288 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "br_gen uart:inst\|br_gen:inst2 " "Info: Elaborating entity \"br_gen\" for hierarchy \"uart:inst\|br_gen:inst2\"" {  } { { "uart.bdf" "inst2" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart.bdf" { { 48 144 272 144 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_transmitter uart:inst\|uart_transmitter:inst1 " "Info: Elaborating entity \"uart_transmitter\" for hierarchy \"uart:inst\|uart_transmitter:inst1\"" {  } { { "uart.bdf" "inst1" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart.bdf" { { -96 312 472 32 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}