uart.tan.qmsg

来自「quatus II 环境下vhdl实现RS232功能」· QMSG 代码 · 共 11 行 · 第 1/5 页

QMSG
11 行
字号
1234
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sel\[0\] register uart:inst\|br_gen:inst2\|ctr3\[2\] register uart:inst\|br_gen:inst2\|ctr3\[2\] 286.7 MHz 3.488 ns Internal " "Info: Clock \"sel\[0\]\" has Internal fmax of 286.7 MHz between source register \"uart:inst\|br_gen:inst2\|ctr3\[2\]\" and destination register \"uart:inst\|br_gen:inst2\|ctr3\[2\]\" (period= 3.488 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.001 ns + Longest register register " "Info: + Longest register to register delay is 2.001 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart:inst\|br_gen:inst2\|ctr3\[2\] 1 REG LC_X14_Y8_N1 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y8_N1; Fanout = 6; REG Node = 'uart:inst\|br_gen:inst2\|ctr3\[2\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "" { uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(1.061 ns) 2.001 ns uart:inst\|br_gen:inst2\|ctr3\[2\] 2 REG LC_X14_Y8_N1 6 " "Info: 2: + IC(0.940 ns) + CELL(1.061 ns) = 2.001 ns; Loc. = LC_X14_Y8_N1; Fanout = 6; REG Node = 'uart:inst\|br_gen:inst2\|ctr3\[2\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "2.001 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.061 ns ( 53.02 % ) " "Info: Total cell delay = 1.061 ns ( 53.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.940 ns ( 46.98 % ) " "Info: Total interconnect delay = 0.940 ns ( 46.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "2.001 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "2.001 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.940ns } { 0.000ns 1.061ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.778 ns - Smallest " "Info: - Smallest clock skew is -0.778 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sel\[0\] destination 12.404 ns + Shortest register " "Info: + Shortest clock path from clock \"sel\[0\]\" to destination register is 12.404 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sel\[0\] 1 CLK PIN_139 3 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_139; Fanout = 3; CLK Node = 'sel\[0\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "" { sel[0] } "NODE_NAME" } } { "uart_test.bdf" "" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_test.bdf" { { 168 32 200 184 "sel\[2..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.253 ns) + CELL(0.914 ns) 5.299 ns uart:inst\|br_gen:inst2\|Mux0~31 2 COMB LC_X11_Y7_N2 2 " "Info: 2: + IC(3.253 ns) + CELL(0.914 ns) = 5.299 ns; Loc. = LC_X11_Y7_N2; Fanout = 2; COMB Node = 'uart:inst\|br_gen:inst2\|Mux0~31'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "4.167 ns" { sel[0] uart:inst|br_gen:inst2|Mux0~31 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.146 ns) + CELL(0.740 ns) 7.185 ns uart:inst\|br_gen:inst2\|Mux0~34 3 COMB LC_X10_Y7_N9 4 " "Info: 3: + IC(1.146 ns) + CELL(0.740 ns) = 7.185 ns; Loc. = LC_X10_Y7_N9; Fanout = 4; COMB Node = 'uart:inst\|br_gen:inst2\|Mux0~34'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "1.886 ns" { uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.301 ns) + CELL(0.918 ns) 12.404 ns uart:inst\|br_gen:inst2\|ctr3\[2\] 4 REG LC_X14_Y8_N1 6 " "Info: 4: + IC(4.301 ns) + CELL(0.918 ns) = 12.404 ns; Loc. = LC_X14_Y8_N1; Fanout = 6; REG Node = 'uart:inst\|br_gen:inst2\|ctr3\[2\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "5.219 ns" { uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.704 ns ( 29.86 % ) " "Info: Total cell delay = 3.704 ns ( 29.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.700 ns ( 70.14 % ) " "Info: Total interconnect delay = 8.700 ns ( 70.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "12.404 ns" { sel[0] uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "12.404 ns" { sel[0] sel[0]~combout uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 3.253ns 1.146ns 4.301ns } { 0.000ns 1.132ns 0.914ns 0.740ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sel\[0\] source 13.182 ns - Longest register " "Info: - Longest clock path from clock \"sel\[0\]\" to source register is 13.182 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sel\[0\] 1 CLK PIN_139 3 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_139; Fanout = 3; CLK Node = 'sel\[0\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "" { sel[0] } "NODE_NAME" } } { "uart_test.bdf" "" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_test.bdf" { { 168 32 200 184 "sel\[2..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.712 ns) + CELL(0.200 ns) 4.044 ns uart:inst\|br_gen:inst2\|Mux0~30 2 COMB LC_X8_Y7_N9 1 " "Info: 2: + IC(2.712 ns) + CELL(0.200 ns) = 4.044 ns; Loc. = LC_X8_Y7_N9; Fanout = 1; COMB Node = 'uart:inst\|br_gen:inst2\|Mux0~30'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "2.912 ns" { sel[0] uart:inst|br_gen:inst2|Mux0~30 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.833 ns) + CELL(0.200 ns) 6.077 ns uart:inst\|br_gen:inst2\|Mux0~31 3 COMB LC_X11_Y7_N2 2 " "Info: 3: + IC(1.833 ns) + CELL(0.200 ns) = 6.077 ns; Loc. = LC_X11_Y7_N2; Fanout = 2; COMB Node = 'uart:inst\|br_gen:inst2\|Mux0~31'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "2.033 ns" { uart:inst|br_gen:inst2|Mux0~30 uart:inst|br_gen:inst2|Mux0~31 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.146 ns) + CELL(0.740 ns) 7.963 ns uart:inst\|br_gen:inst2\|Mux0~34 4 COMB LC_X10_Y7_N9 4 " "Info: 4: + IC(1.146 ns) + CELL(0.740 ns) = 7.963 ns; Loc. = LC_X10_Y7_N9; Fanout = 4; COMB Node = 'uart:inst\|br_gen:inst2\|Mux0~34'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "1.886 ns" { uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.301 ns) + CELL(0.918 ns) 13.182 ns uart:inst\|br_gen:inst2\|ctr3\[2\] 5 REG LC_X14_Y8_N1 6 " "Info: 5: + IC(4.301 ns) + CELL(0.918 ns) = 13.182 ns; Loc. = LC_X14_Y8_N1; Fanout = 6; REG Node = 'uart:inst\|br_gen:inst2\|ctr3\[2\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "5.219 ns" { uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.190 ns ( 24.20 % ) " "Info: Total cell delay = 3.190 ns ( 24.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.992 ns ( 75.80 % ) " "Info: Total interconnect delay = 9.992 ns ( 75.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "13.182 ns" { sel[0] uart:inst|br_gen:inst2|Mux0~30 uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "13.182 ns" { sel[0] sel[0]~combout uart:inst|br_gen:inst2|Mux0~30 uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 2.712ns 1.833ns 1.146ns 4.301ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.740ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "12.404 ns" { sel[0] uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "12.404 ns" { sel[0] sel[0]~combout uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 3.253ns 1.146ns 4.301ns } { 0.000ns 1.132ns 0.914ns 0.740ns 0.918ns } } } { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "13.182 ns" { sel[0] uart:inst|br_gen:inst2|Mux0~30 uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "13.182 ns" { sel[0] sel[0]~combout uart:inst|br_gen:inst2|Mux0~30 uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 2.712ns 1.833ns 1.146ns 4.301ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.740ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "2.001 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "2.001 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.940ns } { 0.000ns 1.061ns } } } { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "12.404 ns" { sel[0] uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "12.404 ns" { sel[0] sel[0]~combout uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 3.253ns 1.146ns 4.301ns } { 0.000ns 1.132ns 0.914ns 0.740ns 0.918ns } } } { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "13.182 ns" { sel[0] uart:inst|br_gen:inst2|Mux0~30 uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "13.182 ns" { sel[0] sel[0]~combout uart:inst|br_gen:inst2|Mux0~30 uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 2.712ns 1.833ns 1.146ns 4.301ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.740ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sel\[1\] register uart:inst\|br_gen:inst2\|ctr3\[2\] register uart:inst\|br_gen:inst2\|ctr3\[2\] 236.13 MHz 4.235 ns Internal " "Info: Clock \"sel\[1\]\" has Internal fmax of 236.13 MHz between source register \"uart:inst\|br_gen:inst2\|ctr3\[2\]\" and destination register \"uart:inst\|br_gen:inst2\|ctr3\[2\]\" (period= 4.235 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.001 ns + Longest register register " "Info: + Longest register to register delay is 2.001 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart:inst\|br_gen:inst2\|ctr3\[2\] 1 REG LC_X14_Y8_N1 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y8_N1; Fanout = 6; REG Node = 'uart:inst\|br_gen:inst2\|ctr3\[2\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "" { uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(1.061 ns) 2.001 ns uart:inst\|br_gen:inst2\|ctr3\[2\] 2 REG LC_X14_Y8_N1 6 " "Info: 2: + IC(0.940 ns) + CELL(1.061 ns) = 2.001 ns; Loc. = LC_X14_Y8_N1; Fanout = 6; REG Node = 'uart:inst\|br_gen:inst2\|ctr3\[2\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "2.001 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.061 ns ( 53.02 % ) " "Info: Total cell delay = 1.061 ns ( 53.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.940 ns ( 46.98 % ) " "Info: Total interconnect delay = 0.940 ns ( 46.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "2.001 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "2.001 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.940ns } { 0.000ns 1.061ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.525 ns - Smallest " "Info: - Smallest clock skew is -1.525 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sel\[1\] destination 12.071 ns + Shortest register " "Info: + Shortest clock path from clock \"sel\[1\]\" to destination register is 12.071 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sel\[1\] 1 CLK PIN_138 3 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_138; Fanout = 3; CLK Node = 'sel\[1\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "" { sel[1] } "NODE_NAME" } } { "uart_test.bdf" "" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_test.bdf" { { 168 32 200 184 "sel\[2..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.275 ns) + CELL(0.740 ns) 5.147 ns uart:inst\|br_gen:inst2\|Mux0~33 2 COMB LC_X11_Y7_N3 2 " "Info: 2: + IC(3.275 ns) + CELL(0.740 ns) = 5.147 ns; Loc. = LC_X11_Y7_N3; Fanout = 2; COMB Node = 'uart:inst\|br_gen:inst2\|Mux0~33'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "4.015 ns" { sel[1] uart:inst|br_gen:inst2|Mux0~33 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.511 ns) 6.852 ns uart:inst\|br_gen:inst2\|Mux0~34 3 COMB LC_X10_Y7_N9 4 " "Info: 3: + IC(1.194 ns) + CELL(0.511 ns) = 6.852 ns; Loc. = LC_X10_Y7_N9; Fanout = 4; COMB Node = 'uart:inst\|br_gen:inst2\|Mux0~34'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "1.705 ns" { uart:inst|br_gen:inst2|Mux0~33 uart:inst|br_gen:inst2|Mux0~34 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.301 ns) + CELL(0.918 ns) 12.071 ns uart:inst\|br_gen:inst2\|ctr3\[2\] 4 REG LC_X14_Y8_N1 6 " "Info: 4: + IC(4.301 ns) + CELL(0.918 ns) = 12.071 ns; Loc. = LC_X14_Y8_N1; Fanout = 6; REG Node = 'uart:inst\|br_gen:inst2\|ctr3\[2\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "5.219 ns" { uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.301 ns ( 27.35 % ) " "Info: Total cell delay = 3.301 ns ( 27.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.770 ns ( 72.65 % ) " "Info: Total interconnect delay = 8.770 ns ( 72.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "12.071 ns" { sel[1] uart:inst|br_gen:inst2|Mux0~33 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "12.071 ns" { sel[1] sel[1]~combout uart:inst|br_gen:inst2|Mux0~33 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 3.275ns 1.194ns 4.301ns } { 0.000ns 1.132ns 0.740ns 0.511ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sel\[1\] source 13.596 ns - Longest register " "Info: - Longest clock path from clock \"sel\[1\]\" to source register is 13.596 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sel\[1\] 1 CLK PIN_138 3 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_138; Fanout = 3; CLK Node = 'sel\[1\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "" { sel[1] } "NODE_NAME" } } { "uart_test.bdf" "" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_test.bdf" { { 168 32 200 184 "sel\[2..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.815 ns) + CELL(0.511 ns) 4.458 ns uart:inst\|br_gen:inst2\|Mux0~30 2 COMB LC_X8_Y7_N9 1 " "Info: 2: + IC(2.815 ns) + CELL(0.511 ns) = 4.458 ns; Loc. = LC_X8_Y7_N9; Fanout = 1; COMB Node = 'uart:inst\|br_gen:inst2\|Mux0~30'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "3.326 ns" { sel[1] uart:inst|br_gen:inst2|Mux0~30 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.833 ns) + CELL(0.200 ns) 6.491 ns uart:inst\|br_gen:inst2\|Mux0~31 3 COMB LC_X11_Y7_N2 2 " "Info: 3: + IC(1.833 ns) + CELL(0.200 ns) = 6.491 ns; Loc. = LC_X11_Y7_N2; Fanout = 2; COMB Node = 'uart:inst\|br_gen:inst2\|Mux0~31'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "2.033 ns" { uart:inst|br_gen:inst2|Mux0~30 uart:inst|br_gen:inst2|Mux0~31 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.146 ns) + CELL(0.740 ns) 8.377 ns uart:inst\|br_gen:inst2\|Mux0~34 4 COMB LC_X10_Y7_N9 4 " "Info: 4: + IC(1.146 ns) + CELL(0.740 ns) = 8.377 ns; Loc. = LC_X10_Y7_N9; Fanout = 4; COMB Node = 'uart:inst\|br_gen:inst2\|Mux0~34'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "1.886 ns" { uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.301 ns) + CELL(0.918 ns) 13.596 ns uart:inst\|br_gen:i
1234

uart.tan.qmsg - 源码说明

本页面展示了「quatus II 环境下vhdl实现RS232功能」中的 uart.tan.qmsg 源码文件，采用 QMSG 编程语言编写，共 11 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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