uart.tan.qmsg

来自「quatus II 环境下vhdl实现RS232功能」· QMSG 代码 · 共 11 行 · 第 1/5 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "15 " "Warning: Found 15 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "uart:inst\|br_gen:inst2\|Mux0~33 " "Info: Detected gated clock \"uart:inst\|br_gen:inst2\|Mux0~33\" as buffer" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } } { "d:/altera/quartus601/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus601/win/Assignment Editor.qase" 1 { { 0 "uart:inst\|br_gen:inst2\|Mux0~33" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "uart:inst\|br_gen:inst2\|Mux0~32 " "Info: Detected gated clock \"uart:inst\|br_gen:inst2\|Mux0~32\" as buffer" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } } { "d:/altera/quartus601/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus601/win/Assignment Editor.qase" 1 { { 0 "uart:inst\|br_gen:inst2\|Mux0~32" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "uart:inst\|br_gen:inst2\|Mux0~31 " "Info: Detected gated clock \"uart:inst\|br_gen:inst2\|Mux0~31\" as buffer" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } } { "d:/altera/quartus601/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus601/win/Assignment Editor.qase" 1 { { 0 "uart:inst\|br_gen:inst2\|Mux0~31" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart:inst\|br_gen:inst2\|ctr2\[7\] " "Info: Detected ripple clock \"uart:inst\|br_gen:inst2\|ctr2\[7\]\" as buffer" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 45 -1 0 } } { "d:/altera/quartus601/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus601/win/Assignment Editor.qase" 1 { { 0 "uart:inst\|br_gen:inst2\|ctr2\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "uart:inst\|br_gen:inst2\|Mux0~30 " "Info: Detected gated clock \"uart:inst\|br_gen:inst2\|Mux0~30\" as buffer" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } } { "d:/altera/quartus601/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus601/win/Assignment Editor.qase" 1 { { 0 "uart:inst\|br_gen:inst2\|Mux0~30" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart:inst\|br_gen:inst2\|ctr2\[1\] " "Info: Detected ripple clock \"uart:inst\|br_gen:inst2\|ctr2\[1\]\" as buffer" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 45 -1 0 } } { "d:/altera/quartus601/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus601/win/Assignment Editor.qase" 1 { { 0 "uart:inst\|br_gen:inst2\|ctr2\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart:inst\|br_gen:inst2\|ctr2\[0\] " "Info: Detected ripple clock \"uart:inst\|br_gen:inst2\|ctr2\[0\]\" as buffer" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 45 -1 0 } } { "d:/altera/quartus601/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus601/win/Assignment Editor.qase" 1 { { 0 "uart:inst\|br_gen:inst2\|ctr2\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart:inst\|br_gen:inst2\|ctr2\[2\] " "Info: Detected ripple clock \"uart:inst\|br_gen:inst2\|ctr2\[2\]\" as buffer" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 45 -1 0 } } { "d:/altera/quartus601/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus601/win/Assignment Editor.qase" 1 { { 0 "uart:inst\|br_gen:inst2\|ctr2\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart:inst\|br_gen:inst2\|ctr2\[3\] " "Info: Detected ripple clock \"uart:inst\|br_gen:inst2\|ctr2\[3\]\" as buffer" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 45 -1 0 } } { "d:/altera/quartus601/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus601/win/Assignment Editor.qase" 1 { { 0 "uart:inst\|br_gen:inst2\|ctr2\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart:inst\|br_gen:inst2\|ctr2\[4\] " "Info: Detected ripple clock \"uart:inst\|br_gen:inst2\|ctr2\[4\]\" as buffer" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 45 -1 0 } } { "d:/altera/quartus601/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus601/win/Assignment Editor.qase" 1 { { 0 "uart:inst\|br_gen:inst2\|ctr2\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart:inst\|br_gen:inst2\|ctr2\[6\] " "Info: Detected ripple clock \"uart:inst\|br_gen:inst2\|ctr2\[6\]\" as buffer" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 45 -1 0 } } { "d:/altera/quartus601/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus601/win/Assignment Editor.qase" 1 { { 0 "uart:inst\|br_gen:inst2\|ctr2\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart:inst\|br_gen:inst2\|cnt2 " "Info: Detected ripple clock \"uart:inst\|br_gen:inst2\|cnt2\" as buffer" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 16 -1 0 } } { "d:/altera/quartus601/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus601/win/Assignment Editor.qase" 1 { { 0 "uart:inst\|br_gen:inst2\|cnt2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart:inst\|br_gen:inst2\|ctr2\[5\] " "Info: Detected ripple clock \"uart:inst\|br_gen:inst2\|ctr2\[5\]\" as buffer" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 45 -1 0 } } { "d:/altera/quartus601/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus601/win/Assignment Editor.qase" 1 { { 0 "uart:inst\|br_gen:inst2\|ctr2\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_div:inst1\|cnt\[13\] " "Info: Detected ripple clock \"clk_div:inst1\|cnt\[13\]\" as buffer" {  } { { "clk_div.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/clk_div.vhd" 18 -1 0 } } { "d:/altera/quartus601/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus601/win/Assignment Editor.qase" 1 { { 0 "clk_div:inst1\|cnt\[13\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "uart:inst\|br_gen:inst2\|Mux0~34 " "Info: Detected gated clock \"uart:inst\|br_gen:inst2\|Mux0~34\" as buffer" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } } { "d:/altera/quartus601/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus601/win/Assignment Editor.qase" 1 { { 0 "uart:inst\|br_gen:inst2\|Mux0~34" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register uart:inst\|br_gen:inst2\|ctr3\[2\] register uart:inst\|uart_transmitter:inst1\|bct\[1\] 45.09 MHz 22.177 ns Internal " "Info: Clock \"clk\" has Internal fmax of 45.09 MHz between source register \"uart:inst\|br_gen:inst2\|ctr3\[2\]\" and destination register \"uart:inst\|uart_transmitter:inst1\|bct\[1\]\" (period= 22.177 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.597 ns + Longest register register " "Info: + Longest register to register delay is 5.597 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart:inst\|br_gen:inst2\|ctr3\[2\] 1 REG LC_X14_Y8_N1 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y8_N1; Fanout = 6; REG Node = 'uart:inst\|br_gen:inst2\|ctr3\[2\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "" { uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.941 ns) + CELL(0.200 ns) 1.141 ns uart:inst\|uart_transmitter:inst1\|inc~36 2 COMB LC_X14_Y8_N0 4 " "Info: 2: + IC(0.941 ns) + CELL(0.200 ns) = 1.141 ns; Loc. = LC_X14_Y8_N0; Fanout = 4; COMB Node = 'uart:inst\|uart_transmitter:inst1\|inc~36'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "1.141 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|uart_transmitter:inst1|inc~36 } "NODE_NAME" } } { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.714 ns) + CELL(0.747 ns) 2.602 ns uart:inst\|uart_transmitter:inst1\|Add0~62 3 COMB LC_X14_Y8_N6 2 " "Info: 3: + IC(0.714 ns) + CELL(0.747 ns) = 2.602 ns; Loc. = LC_X14_Y8_N6; Fanout = 2; COMB Node = 'uart:inst\|uart_transmitter:inst1\|Add0~62'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "1.461 ns" { uart:inst|uart_transmitter:inst1|inc~36 uart:inst|uart_transmitter:inst1|Add0~62 } "NODE_NAME" } } { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.815 ns) 3.417 ns uart:inst\|uart_transmitter:inst1\|Add0~57 4 COMB LC_X14_Y8_N7 1 " "Info: 4: + IC(0.000 ns) + CELL(0.815 ns) = 3.417 ns; Loc. = LC_X14_Y8_N7; Fanout = 1; COMB Node = 'uart:inst\|uart_transmitter:inst1\|Add0~57'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "0.815 ns" { uart:inst|uart_transmitter:inst1|Add0~62 uart:inst|uart_transmitter:inst1|Add0~57 } "NODE_NAME" } } { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(0.280 ns) 5.597 ns uart:inst\|uart_transmitter:inst1\|bct\[1\] 5 REG LC_X13_Y8_N7 4 " "Info: 5: + IC(1.900 ns) + CELL(0.280 ns) = 5.597 ns; Loc. = LC_X13_Y8_N7; Fanout = 4; REG Node = 'uart:inst\|uart_transmitter:inst1\|bct\[1\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "2.180 ns" { uart:inst|uart_transmitter:inst1|Add0~57 uart:inst|uart_transmitter:inst1|bct[1] } "NODE_NAME" } } { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.042 ns ( 36.48 % ) " "Info: Total cell delay = 2.042 ns ( 36.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.555 ns ( 63.52 % ) " "Info: Total interconnect delay = 3.555 ns ( 63.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "5.597 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|uart_transmitter:inst1|inc~36 uart:inst|uart_transmitter:inst1|Add0~62 uart:inst|uart_transmitter:inst1|Add0~57 uart:inst|uart_transmitter:inst1|bct[1] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "5.597 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|uart_transmitter:inst1|inc~36 uart:inst|uart_transmitter:inst1|Add0~62 uart:inst|uart_transmitter:inst1|Add0~57 uart:inst|uart_transmitter:inst1|bct[1] } { 0.000ns 0.941ns 0.714ns 0.000ns 1.900ns } { 0.000ns 0.200ns 0.747ns 0.815ns 0.280ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-15.871 ns - Smallest " "Info: - Smallest clock skew is -15.871 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 93 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 93; CLK Node = 'clk'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_test.bdf" "" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_test.bdf" { { 136 32 200 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns uart:inst\|uart_transmitter:inst1\|bct\[1\] 2 REG LC_X13_Y8_N7 4 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X13_Y8_N7; Fanout = 4; REG Node = 'uart:inst\|uart_transmitter:inst1\|bct\[1\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "2.656 ns" { clk uart:inst|uart_transmitter:inst1|bct[1] } "NODE_NAME" } } { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk uart:inst|uart_transmitter:inst1|bct[1] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout uart:inst|uart_transmitter:inst1|bct[1] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 19.690 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 19.690 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 93 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 93; CLK Node = 'clk'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_test.bdf" "" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_test.bdf" { { 136 32 200 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns uart:inst\|br_gen:inst2\|cnt2 2 REG LC_X12_Y3_N2 9 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N2; Fanout = 9; REG Node = 'uart:inst\|br_gen:inst2\|cnt2'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "3.032 ns" { clk uart:inst|br_gen:inst2|cnt2 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(1.294 ns) 8.517 ns uart:inst\|br_gen:inst2\|ctr2\[4\] 3 REG LC_X8_Y7_N4 3 " "Info: 3: + IC(3.028 ns) + CELL(1.294 ns) = 8.517 ns; Loc. = LC_X8_Y7_N4; Fanout = 3; REG Node = 'uart:inst\|br_gen:inst2\|ctr2\[4\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "4.322 ns" { uart:inst|br_gen:inst2|cnt2 uart:inst|br_gen:inst2|ctr2[4] } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.295 ns) + CELL(0.740 ns) 10.552 ns uart:inst\|br_gen:inst2\|Mux0~30 4 COMB LC_X8_Y7_N9 1 " "Info: 4: + IC(1.295 ns) + CELL(0.740 ns) = 10.552 ns; Loc. = LC_X8_Y7_N9; Fanout = 1; COMB Node = 'uart:inst\|br_gen:inst2\|Mux0~30'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "2.035 ns" { uart:inst|br_gen:inst2|ctr2[4] uart:inst|br_gen:inst2|Mux0~30 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.833 ns) + CELL(0.200 ns) 12.585 ns uart:inst\|br_gen:inst2\|Mux0~31 5 COMB LC_X11_Y7_N2 2 " "Info: 5: + IC(1.833 ns) + CELL(0.200 ns) = 12.585 ns; Loc. = LC_X11_Y7_N2; Fanout = 2; COMB Node = 'uart:inst\|br_gen:inst2\|Mux0~31'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "2.033 ns" { uart:inst|br_gen:inst2|Mux0~30 uart:inst|br_gen:inst2|Mux0~31 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.146 ns) + CELL(0.740 ns) 14.471 ns uart:inst\|br_gen:inst2\|Mux0~34 6 COMB LC_X10_Y7_N9 4 " "Info: 6: + IC(1.146 ns) + CELL(0.740 ns) = 14.471 ns; Loc. = LC_X10_Y7_N9; Fanout = 4; COMB Node = 'uart:inst\|br_gen:inst2\|Mux0~34'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "1.886 ns" { uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.301 ns) + CELL(0.918 ns) 19.690 ns uart:inst\|br_gen:inst2\|ctr3\[2\] 7 REG LC_X14_Y8_N1 6 " "Info: 7: + IC(4.301 ns) + CELL(0.918 ns) = 19.690 ns; Loc. = LC_X14_Y8_N1; Fanout = 6; REG Node = 'uart:inst\|br_gen:inst2\|ctr3\[2\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "5.219 ns" { uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.349 ns ( 32.24 % ) " "Info: Total cell delay = 6.349 ns ( 32.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.341 ns ( 67.76 % ) " "Info: Total interconnect delay = 13.341 ns ( 67.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "19.690 ns" { clk uart:inst|br_gen:inst2|cnt2 uart:inst|br_gen:inst2|ctr2[4] uart:inst|br_gen:inst2|Mux0~30 uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "19.690 ns" { clk clk~combout uart:inst|br_gen:inst2|cnt2 uart:inst|br_gen:inst2|ctr2[4] uart:inst|br_gen:inst2|Mux0~30 uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 1.738ns 3.028ns 1.295ns 1.833ns 1.146ns 4.301ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.740ns 0.200ns 0.740ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk uart:inst|uart_transmitter:inst1|bct[1] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout uart:inst|uart_transmitter:inst1|bct[1] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "19.690 ns" { clk uart:inst|br_gen:inst2|cnt2 uart:inst|br_gen:inst2|ctr2[4] uart:inst|br_gen:inst2|Mux0~30 uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "19.690 ns" { clk clk~combout uart:inst|br_gen:inst2|cnt2 uart:inst|br_gen:inst2|ctr2[4] uart:inst|br_gen:inst2|Mux0~30 uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 1.738ns 3.028ns 1.295ns 1.833ns 1.146ns 4.301ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.740ns 0.200ns 0.740ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "uart_transmitter.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_transmitter.vhd" 68 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "5.597 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|uart_transmitter:inst1|inc~36 uart:inst|uart_transmitter:inst1|Add0~62 uart:inst|uart_transmitter:inst1|Add0~57 uart:inst|uart_transmitter:inst1|bct[1] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "5.597 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|uart_transmitter:inst1|inc~36 uart:inst|uart_transmitter:inst1|Add0~62 uart:inst|uart_transmitter:inst1|Add0~57 uart:inst|uart_transmitter:inst1|bct[1] } { 0.000ns 0.941ns 0.714ns 0.000ns 1.900ns } { 0.000ns 0.200ns 0.747ns 0.815ns 0.280ns } } } { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "3.819 ns" { clk uart:inst|uart_transmitter:inst1|bct[1] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout uart:inst|uart_transmitter:inst1|bct[1] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "19.690 ns" { clk uart:inst|br_gen:inst2|cnt2 uart:inst|br_gen:inst2|ctr2[4] uart:inst|br_gen:inst2|Mux0~30 uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "19.690 ns" { clk clk~combout uart:inst|br_gen:inst2|cnt2 uart:inst|br_gen:inst2|ctr2[4] uart:inst|br_gen:inst2|Mux0~30 uart:inst|br_gen:inst2|Mux0~31 uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 1.738ns 3.028ns 1.295ns 1.833ns 1.146ns 4.301ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.740ns 0.200ns 0.740ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "sel\[2\] register register uart:inst\|br_gen:inst2\|ctr3\[2\] uart:inst\|br_gen:inst2\|ctr3\[2\] 304.04 MHz Internal " "Info: Clock \"sel\[2\]\" Internal fmax is restricted to 304.04 MHz between source register \"uart:inst\|br_gen:inst2\|ctr3\[2\]\" and destination register \"uart:inst\|br_gen:inst2\|ctr3\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 3.289 ns " "Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.001 ns + Longest register register " "Info: + Longest register to register delay is 2.001 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart:inst\|br_gen:inst2\|ctr3\[2\] 1 REG LC_X14_Y8_N1 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y8_N1; Fanout = 6; REG Node = 'uart:inst\|br_gen:inst2\|ctr3\[2\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "" { uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(1.061 ns) 2.001 ns uart:inst\|br_gen:inst2\|ctr3\[2\] 2 REG LC_X14_Y8_N1 6 " "Info: 2: + IC(0.940 ns) + CELL(1.061 ns) = 2.001 ns; Loc. = LC_X14_Y8_N1; Fanout = 6; REG Node = 'uart:inst\|br_gen:inst2\|ctr3\[2\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "2.001 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.061 ns ( 53.02 % ) " "Info: Total cell delay = 1.061 ns ( 53.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.940 ns ( 46.98 % ) " "Info: Total interconnect delay = 0.940 ns ( 46.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "2.001 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "2.001 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.940ns } { 0.000ns 1.061ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sel\[2\] destination 10.252 ns + Shortest register " "Info: + Shortest clock path from clock \"sel\[2\]\" to destination register is 10.252 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sel\[2\] 1 CLK PIN_4 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_4; Fanout = 2; CLK Node = 'sel\[2\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "" { sel[2] } "NODE_NAME" } } { "uart_test.bdf" "" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_test.bdf" { { 168 32 200 184 "sel\[2..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.701 ns) + CELL(0.200 ns) 5.033 ns uart:inst\|br_gen:inst2\|Mux0~34 2 COMB LC_X10_Y7_N9 4 " "Info: 2: + IC(3.701 ns) + CELL(0.200 ns) = 5.033 ns; Loc. = LC_X10_Y7_N9; Fanout = 4; COMB Node = 'uart:inst\|br_gen:inst2\|Mux0~34'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "3.901 ns" { sel[2] uart:inst|br_gen:inst2|Mux0~34 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.301 ns) + CELL(0.918 ns) 10.252 ns uart:inst\|br_gen:inst2\|ctr3\[2\] 3 REG LC_X14_Y8_N1 6 " "Info: 3: + IC(4.301 ns) + CELL(0.918 ns) = 10.252 ns; Loc. = LC_X14_Y8_N1; Fanout = 6; REG Node = 'uart:inst\|br_gen:inst2\|ctr3\[2\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "5.219 ns" { uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.250 ns ( 21.95 % ) " "Info: Total cell delay = 2.250 ns ( 21.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.002 ns ( 78.05 % ) " "Info: Total interconnect delay = 8.002 ns ( 78.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "10.252 ns" { sel[2] uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "10.252 ns" { sel[2] sel[2]~combout uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 3.701ns 4.301ns } { 0.000ns 1.132ns 0.200ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sel\[2\] source 10.252 ns - Longest register " "Info: - Longest clock path from clock \"sel\[2\]\" to source register is 10.252 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sel\[2\] 1 CLK PIN_4 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_4; Fanout = 2; CLK Node = 'sel\[2\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "" { sel[2] } "NODE_NAME" } } { "uart_test.bdf" "" { Schematic "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart_test.bdf" { { 168 32 200 184 "sel\[2..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.701 ns) + CELL(0.200 ns) 5.033 ns uart:inst\|br_gen:inst2\|Mux0~34 2 COMB LC_X10_Y7_N9 4 " "Info: 2: + IC(3.701 ns) + CELL(0.200 ns) = 5.033 ns; Loc. = LC_X10_Y7_N9; Fanout = 4; COMB Node = 'uart:inst\|br_gen:inst2\|Mux0~34'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "3.901 ns" { sel[2] uart:inst|br_gen:inst2|Mux0~34 } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.301 ns) + CELL(0.918 ns) 10.252 ns uart:inst\|br_gen:inst2\|ctr3\[2\] 3 REG LC_X14_Y8_N1 6 " "Info: 3: + IC(4.301 ns) + CELL(0.918 ns) = 10.252 ns; Loc. = LC_X14_Y8_N1; Fanout = 6; REG Node = 'uart:inst\|br_gen:inst2\|ctr3\[2\]'" {  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "5.219 ns" { uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.250 ns ( 21.95 % ) " "Info: Total cell delay = 2.250 ns ( 21.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.002 ns ( 78.05 % ) " "Info: Total interconnect delay = 8.002 ns ( 78.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "10.252 ns" { sel[2] uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "10.252 ns" { sel[2] sel[2]~combout uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 3.701ns 4.301ns } { 0.000ns 1.132ns 0.200ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "10.252 ns" { sel[2] uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "10.252 ns" { sel[2] sel[2]~combout uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 3.701ns 4.301ns } { 0.000ns 1.132ns 0.200ns 0.918ns } } } { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "10.252 ns" { sel[2] uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "10.252 ns" { sel[2] sel[2]~combout uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 3.701ns 4.301ns } { 0.000ns 1.132ns 0.200ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "2.001 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "2.001 ns" { uart:inst|br_gen:inst2|ctr3[2] uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.940ns } { 0.000ns 1.061ns } } } { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "10.252 ns" { sel[2] uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "10.252 ns" { sel[2] sel[2]~combout uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 3.701ns 4.301ns } { 0.000ns 1.132ns 0.200ns 0.918ns } } } { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "10.252 ns" { sel[2] uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "10.252 ns" { sel[2] sel[2]~combout uart:inst|br_gen:inst2|Mux0~34 uart:inst|br_gen:inst2|ctr3[2] } { 0.000ns 0.000ns 3.701ns 4.301ns } { 0.000ns 1.132ns 0.200ns 0.918ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus601/win/TimingClosureFloorplan.fld" "" "" { uart:inst|br_gen:inst2|ctr3[2] } "NODE_NAME" } } { "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus601/win/Technology_Viewer.qrui" "" { uart:inst|br_gen:inst2|ctr3[2] } {  } {  } } } { "br_gen.vhd" "" { Text "F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/br_gen.vhd" 55 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}