uart.map.rpt

来自「quatus II 环境下vhdl实现RS232功能」· RPT 代码 · 共 407 行 · 第 1/2 页

+----------------------+-----------------+----------------------+------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 114   ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 72    ;
; Number of registers using Asynchronous Load  ; 10    ;
; Number of registers using Clock Enable       ; 46    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------+
; Inverted Register Statistics                          ;
+---------------------------------------------+---------+
; Inverted Register                           ; Fan out ;
+---------------------------------------------+---------+
; uart:inst|uart_transmitter:inst1|tsr[0]     ; 2       ;
; uart:inst|uart_transmitter:inst1|state.idle ; 2       ;
; uart:inst|uart_transmitter:inst1|tsr[1]     ; 1       ;
; uart:inst|uart_transmitter:inst1|tsr[2]     ; 1       ;
; uart:inst|uart_receiver:inst|RDR[0]         ; 3       ;
; uart:inst|uart_receiver:inst|RDR[5]         ; 3       ;
; uart:inst|uart_receiver:inst|RDR[1]         ; 3       ;
; uart:inst|uart_receiver:inst|RDR[3]         ; 3       ;
; uart:inst|uart_receiver:inst|state.idle     ; 1       ;
; uart:inst|uart_transmitter:inst1|tsr[3]     ; 1       ;
; uart:inst|uart_transmitter:inst1|tsr[4]     ; 1       ;
; uart:inst|uart_transmitter:inst1|tsr[5]     ; 1       ;
; uart:inst|uart_transmitter:inst1|tsr[6]     ; 1       ;
; uart:inst|uart_transmitter:inst1|tsr[7]     ; 1       ;
; uart:inst|uart_transmitter:inst1|tsr[8]     ; 2       ;
; Total number of inverted registers = 15     ;         ;
+---------------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------+
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |uart_test|scan:inst6|bin[3]                        ;
; 4:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |uart_test|uart:inst|uart_transmitter:inst1|tsr[3]  ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |uart_test|uart:inst|uart_receiver:inst|clr1~1      ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |uart_test|uart:inst|uart_receiver:inst|nextstate~5 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------+


+------------------------------------------------------+
; Source assignments for uart:inst|uart_receiver:inst  ;
+----------------+-------+------+----------------------+
; Assignment     ; Value ; From ; To                   ;
+----------------+-------+------+----------------------+
; POWER_UP_LEVEL ; Low   ; -    ; ct2[0]               ;
; POWER_UP_LEVEL ; Low   ; -    ; ct2[1]               ;
; POWER_UP_LEVEL ; Low   ; -    ; ct2[2]               ;
; POWER_UP_LEVEL ; Low   ; -    ; ct2[3]               ;
; POWER_UP_LEVEL ; Low   ; -    ; ct1[0]               ;
; POWER_UP_LEVEL ; Low   ; -    ; ct1[1]               ;
; POWER_UP_LEVEL ; Low   ; -    ; ct1[2]               ;
; POWER_UP_LEVEL ; Low   ; -    ; state.recv_data      ;
; POWER_UP_LEVEL ; Low   ; -    ; state.start_detected ;
; POWER_UP_LEVEL ; High  ; -    ; state.idle           ;
+----------------+-------+------+----------------------+


+-----------------------------------------------+
; Source assignments for uart:inst|br_gen:inst2 ;
+----------------+-------+------+---------------+
; Assignment     ; Value ; From ; To            ;
+----------------+-------+------+---------------+
; POWER_UP_LEVEL ; Low   ; -    ; ctr3[2]       ;
; POWER_UP_LEVEL ; Low   ; -    ; ctr3[1]       ;
; POWER_UP_LEVEL ; Low   ; -    ; ctr3[0]       ;
; POWER_UP_LEVEL ; Low   ; -    ; ctr2[0]       ;
; POWER_UP_LEVEL ; Low   ; -    ; ctr2[1]       ;
; POWER_UP_LEVEL ; Low   ; -    ; ctr2[2]       ;
; POWER_UP_LEVEL ; Low   ; -    ; ctr2[3]       ;
; POWER_UP_LEVEL ; Low   ; -    ; ctr2[4]       ;
; POWER_UP_LEVEL ; Low   ; -    ; ctr2[5]       ;
; POWER_UP_LEVEL ; Low   ; -    ; ctr2[6]       ;
; POWER_UP_LEVEL ; Low   ; -    ; ctr2[7]       ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[0]       ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[1]       ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[2]       ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[3]       ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[4]       ;
+----------------+-------+------+---------------+


+---------------------------------------------------------+
; Source assignments for uart:inst|uart_transmitter:inst1 ;
+----------------+-------+------+-------------------------+
; Assignment     ; Value ; From ; To                      ;
+----------------+-------+------+-------------------------+
; POWER_UP_LEVEL ; Low   ; -    ; bct[0]                  ;
; POWER_UP_LEVEL ; Low   ; -    ; bct[1]                  ;
; POWER_UP_LEVEL ; Low   ; -    ; bct[2]                  ;
; POWER_UP_LEVEL ; Low   ; -    ; bct[3]                  ;
; POWER_UP_LEVEL ; Low   ; -    ; state.tdata             ;
; POWER_UP_LEVEL ; Low   ; -    ; state.synch             ;
; POWER_UP_LEVEL ; High  ; -    ; state.idle              ;
+----------------+-------+------+-------------------------+


+----------------------------------------+
; Source assignments for scan:inst6      ;
+----------------+-------+------+--------+
; Assignment     ; Value ; From ; To     ;
+----------------+-------+------+--------+
; POWER_UP_LEVEL ; Low   ; -    ; sel[0] ;
; POWER_UP_LEVEL ; Low   ; -    ; sel[1] ;
+----------------+-------+------+--------+


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart:inst|br_gen:inst2 ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type                                       ;
+----------------+-------+--------------------------------------------+
; divisor        ; 26    ; Untyped                                    ;
+----------------+-------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Jan 07 10:42:19 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart -c uart
Info: Found 2 design units, including 1 entities, in source file br_gen.vhd
    Info: Found design unit 1: br_gen-arch
    Info: Found entity 1: br_gen
Warning: Can't analyze file -- file F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/uart.vhd is missing
Info: Found 2 design units, including 1 entities, in source file uart_receiver.vhd
    Info: Found design unit 1: uart_receiver-arch
    Info: Found entity 1: uart_receiver
Info: Found 2 design units, including 1 entities, in source file uart_transmitter.vhd
    Info: Found design unit 1: uart_transmitter-arch
    Info: Found entity 1: uart_transmitter
Info: Found 1 design units, including 1 entities, in source file uart_test.bdf
    Info: Found entity 1: uart_test
Info: Found 2 design units, including 1 entities, in source file clk_div.vhd
    Info: Found design unit 1: clk_div-a
    Info: Found entity 1: clk_div
Info: Found 2 design units, including 1 entities, in source file scan.vhd
    Info: Found design unit 1: scan-arch
    Info: Found entity 1: scan
Warning: Can't analyze file -- file F:/Quartus/Quartus_II5.0/SOURCE/RS232/RS232/Block1.bdf is missing
Info: Found 1 design units, including 1 entities, in source file uart.bdf
    Info: Found entity 1: uart
Info: Elaborating entity "uart_test" for the top level hierarchy
Info: Elaborating entity "uart" for hierarchy "uart:inst"
Info: Elaborating entity "uart_receiver" for hierarchy "uart:inst|uart_receiver:inst"
Info: Elaborating entity "br_gen" for hierarchy "uart:inst|br_gen:inst2"
Info: Elaborating entity "uart_transmitter" for hierarchy "uart:inst|uart_transmitter:inst1"
Info: Elaborating entity "scan" for hierarchy "scan:inst6"
Warning (10492): VHDL Process Statement warning at scan.vhd(26): signal "rxd_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at scan.vhd(27): signal "rxd_data" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "clk_div" for hierarchy "clk_div:inst1"
Warning (10492): VHDL Process Statement warning at clk_div.vhd(18): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: State machine "|uart_test|uart:inst|uart_transmitter:inst1|state" contains 3 states
Info: State machine "|uart_test|uart:inst|uart_receiver:inst|state" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|uart_test|uart:inst|uart_transmitter:inst1|state"
Info: Encoding result for state machine "|uart_test|uart:inst|uart_transmitter:inst1|state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "uart:inst|uart_transmitter:inst1|state.tdata"
        Info: Encoded state bit "uart:inst|uart_transmitter:inst1|state.synch"
        Info: Encoded state bit "uart:inst|uart_transmitter:inst1|state.idle"
    Info: State "|uart_test|uart:inst|uart_transmitter:inst1|state.idle" uses code string "000"
    Info: State "|uart_test|uart:inst|uart_transmitter:inst1|state.synch" uses code string "011"
    Info: State "|uart_test|uart:inst|uart_transmitter:inst1|state.tdata" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|uart_test|uart:inst|uart_receiver:inst|state"
Info: Encoding result for state machine "|uart_test|uart:inst|uart_receiver:inst|state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "uart:inst|uart_receiver:inst|state.recv_data"
        Info: Encoded state bit "uart:inst|uart_receiver:inst|state.start_detected"
        Info: Encoded state bit "uart:inst|uart_receiver:inst|state.idle"
    Info: State "|uart_test|uart:inst|uart_receiver:inst|state.idle" uses code string "000"
    Info: State "|uart_test|uart:inst|uart_receiver:inst|state.start_detected" uses code string "011"
    Info: State "|uart_test|uart:inst|uart_receiver:inst|state.recv_data" uses code string "101"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "seven_seg[7]" stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 204 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 15 output pins
    Info: Implemented 182 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
    Info: Processing ended: Mon Jan 07 10:42:22 2008
    Info: Elapsed time: 00:00:04