adcint.fit.qmsg

用FPGA实现的ADC采样器

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.906 ns register register " "Info: Estimated most critical path is register to register delay of 0.906 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.st2 1 REG LAB_X8_Y6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y6; Fanout = 2; REG Node = 'current_state.st2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "" { current_state.st2 } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.299 ns) + CELL(0.607 ns) 0.906 ns current_state.st2 2 REG LAB_X8_Y6 2 " "Info: 2: + IC(0.299 ns) + CELL(0.607 ns) = 0.906 ns; Loc. = LAB_X8_Y6; Fanout = 2; REG Node = 'current_state.st2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "0.906 ns" { current_state.st2 current_state.st2 } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns ( 67.00 % ) " "Info: Total cell delay = 0.607 ns ( 67.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.299 ns ( 33.00 % ) " "Info: Total interconnect delay = 0.299 ns ( 33.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "0.906 ns" { current_state.st2 current_state.st2 } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ADDA VCC " "Info: Pin ADDA has VCC driving its datain port" {  } { { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 10 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ADDA" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "" { ADDA } "NODE_NAME" } "" } } { "F:/zonghesheji/EXP/ADC/ADCINT.fld" "" { Floorplan "F:/zonghesheji/EXP/ADC/ADCINT.fld" "" "" { ADDA } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 18 21:22:06 2006 " "Info: Processing ended: Mon Dec 18 21:22:06 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}