adcint.tan.qmsg

用FPGA实现的ADC采样器

{ "Info" "ITDB_TH_RESULT" "REGL\[5\] D\[5\] CLK 1.047 ns register " "Info: th for register \"REGL\[5\]\" (data pin = \"D\[5\]\", clock pin = \"CLK\") is 1.047 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.183 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 7.183 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "" { CLK } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.935 ns) 2.962 ns current_state.st4 2 REG LC_X8_Y6_N2 11 " "Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X8_Y6_N2; Fanout = 11; REG Node = 'current_state.st4'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "1.493 ns" { CLK current_state.st4 } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.510 ns) + CELL(0.711 ns) 7.183 ns REGL\[5\] 3 REG LC_X26_Y11_N2 1 " "Info: 3: + IC(3.510 ns) + CELL(0.711 ns) = 7.183 ns; Loc. = LC_X26_Y11_N2; Fanout = 1; REG Node = 'REGL\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "4.221 ns" { current_state.st4 REGL[5] } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.37 % ) " "Info: Total cell delay = 3.115 ns ( 43.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.068 ns ( 56.63 % ) " "Info: Total interconnect delay = 4.068 ns ( 56.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "7.183 ns" { CLK current_state.st4 REGL[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.183 ns" { CLK CLK~out0 current_state.st4 REGL[5] } { 0.000ns 0.000ns 0.558ns 3.510ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 44 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.151 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.151 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns D\[5\] 1 PIN PIN_103 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_103; Fanout = 1; PIN Node = 'D\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "" { D[5] } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.567 ns) + CELL(0.115 ns) 6.151 ns REGL\[5\] 2 REG LC_X26_Y11_N2 1 " "Info: 2: + IC(4.567 ns) + CELL(0.115 ns) = 6.151 ns; Loc. = LC_X26_Y11_N2; Fanout = 1; REG Node = 'REGL\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "4.682 ns" { D[5] REGL[5] } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 25.75 % ) " "Info: Total cell delay = 1.584 ns ( 25.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.567 ns ( 74.25 % ) " "Info: Total interconnect delay = 4.567 ns ( 74.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "6.151 ns" { D[5] REGL[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.151 ns" { D[5] D[5]~out0 REGL[5] } { 0.000ns 0.000ns 4.567ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "7.183 ns" { CLK current_state.st4 REGL[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.183 ns" { CLK CLK~out0 current_state.st4 REGL[5] } { 0.000ns 0.000ns 0.558ns 3.510ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "6.151 ns" { D[5] REGL[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.151 ns" { D[5] D[5]~out0 REGL[5] } { 0.000ns 0.000ns 4.567ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 18 21:22:13 2006 " "Info: Processing ended: Mon Dec 18 21:22:13 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}