adcint.tan.qmsg

用FPGA实现的ADC采样器

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "current_state.st4 " "Info: Detected ripple clock \"current_state.st4\" as buffer" {  } { { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 40 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "current_state.st4" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register current_state.st2 current_state.st2 275.03 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 275.03 MHz between source register \"current_state.st2\" and destination register \"current_state.st2\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.040 ns + Longest register register " "Info: + Longest register to register delay is 1.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.st2 1 REG LC_X8_Y6_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.st2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "" { current_state.st2 } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.562 ns) + CELL(0.478 ns) 1.040 ns current_state.st2 2 REG LC_X8_Y6_N8 2 " "Info: 2: + IC(0.562 ns) + CELL(0.478 ns) = 1.040 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.st2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "1.040 ns" { current_state.st2 current_state.st2 } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns ( 45.96 % ) " "Info: Total cell delay = 0.478 ns ( 45.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.562 ns ( 54.04 % ) " "Info: Total interconnect delay = 0.562 ns ( 54.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "1.040 ns" { current_state.st2 current_state.st2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.040 ns" { current_state.st2 current_state.st2 } { 0.000ns 0.562ns } { 0.000ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.738 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "" { CLK } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.711 ns) 2.738 ns current_state.st2 2 REG LC_X8_Y6_N8 2 " "Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.st2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "1.269 ns" { CLK current_state.st2 } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.62 % ) " "Info: Total cell delay = 2.180 ns ( 79.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.558 ns ( 20.38 % ) " "Info: Total interconnect delay = 0.558 ns ( 20.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "2.738 ns" { CLK current_state.st2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { CLK CLK~out0 current_state.st2 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.738 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "" { CLK } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.711 ns) 2.738 ns current_state.st2 2 REG LC_X8_Y6_N8 2 " "Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.st2'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "1.269 ns" { CLK current_state.st2 } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.62 % ) " "Info: Total cell delay = 2.180 ns ( 79.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.558 ns ( 20.38 % ) " "Info: Total interconnect delay = 0.558 ns ( 20.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "2.738 ns" { CLK current_state.st2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { CLK CLK~out0 current_state.st2 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "2.738 ns" { CLK current_state.st2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { CLK CLK~out0 current_state.st2 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "2.738 ns" { CLK current_state.st2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { CLK CLK~out0 current_state.st2 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 40 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 40 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "1.040 ns" { current_state.st2 current_state.st2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.040 ns" { current_state.st2 current_state.st2 } { 0.000ns 0.562ns } { 0.000ns 0.478ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "2.738 ns" { CLK current_state.st2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { CLK CLK~out0 current_state.st2 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "2.738 ns" { CLK current_state.st2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { CLK CLK~out0 current_state.st2 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "" { current_state.st2 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { current_state.st2 } {  } {  } } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 40 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "current_state.st3 EOC CLK 4.838 ns register " "Info: tsu for register \"current_state.st3\" (data pin = \"EOC\", clock pin = \"CLK\") is 4.838 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.539 ns + Longest pin register " "Info: + Longest pin to register delay is 7.539 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns EOC 1 PIN PIN_49 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_49; Fanout = 2; PIN Node = 'EOC'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "" { EOC } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.457 ns) + CELL(0.607 ns) 7.539 ns current_state.st3 2 REG LC_X8_Y6_N4 2 " "Info: 2: + IC(5.457 ns) + CELL(0.607 ns) = 7.539 ns; Loc. = LC_X8_Y6_N4; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "6.064 ns" { EOC current_state.st3 } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.082 ns ( 27.62 % ) " "Info: Total cell delay = 2.082 ns ( 27.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.457 ns ( 72.38 % ) " "Info: Total interconnect delay = 5.457 ns ( 72.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "7.539 ns" { EOC current_state.st3 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.539 ns" { EOC EOC~out0 current_state.st3 } { 0.000ns 0.000ns 5.457ns } { 0.000ns 1.475ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 40 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.738 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "" { CLK } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.711 ns) 2.738 ns current_state.st3 2 REG LC_X8_Y6_N4 2 " "Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X8_Y6_N4; Fanout = 2; REG Node = 'current_state.st3'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "1.269 ns" { CLK current_state.st3 } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.62 % ) " "Info: Total cell delay = 2.180 ns ( 79.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.558 ns ( 20.38 % ) " "Info: Total interconnect delay = 0.558 ns ( 20.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "2.738 ns" { CLK current_state.st3 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { CLK CLK~out0 current_state.st3 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "7.539 ns" { EOC current_state.st3 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.539 ns" { EOC EOC~out0 current_state.st3 } { 0.000ns 0.000ns 5.457ns } { 0.000ns 1.475ns 0.607ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "2.738 ns" { CLK current_state.st3 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.738 ns" { CLK CLK~out0 current_state.st3 } { 0.000ns 0.000ns 0.558ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK Q\[0\] REGL\[0\] 11.248 ns register " "Info: tco from clock \"CLK\" to destination pin \"Q\[0\]\" through register \"REGL\[0\]\" is 11.248 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.130 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 7.130 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "" { CLK } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.935 ns) 2.962 ns current_state.st4 2 REG LC_X8_Y6_N2 11 " "Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X8_Y6_N2; Fanout = 11; REG Node = 'current_state.st4'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "1.493 ns" { CLK current_state.st4 } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.457 ns) + CELL(0.711 ns) 7.130 ns REGL\[0\] 3 REG LC_X7_Y1_N2 1 " "Info: 3: + IC(3.457 ns) + CELL(0.711 ns) = 7.130 ns; Loc. = LC_X7_Y1_N2; Fanout = 1; REG Node = 'REGL\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "4.168 ns" { current_state.st4 REGL[0] } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 43.69 % ) " "Info: Total cell delay = 3.115 ns ( 43.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.015 ns ( 56.31 % ) " "Info: Total interconnect delay = 4.015 ns ( 56.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "7.130 ns" { CLK current_state.st4 REGL[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.130 ns" { CLK CLK~out0 current_state.st4 REGL[0] } { 0.000ns 0.000ns 0.558ns 3.457ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 44 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.894 ns + Longest register pin " "Info: + Longest register to pin delay is 3.894 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REGL\[0\] 1 REG LC_X7_Y1_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y1_N2; Fanout = 1; REG Node = 'REGL\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "" { REGL[0] } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.770 ns) + CELL(2.124 ns) 3.894 ns Q\[0\] 2 PIN PIN_36 0 " "Info: 2: + IC(1.770 ns) + CELL(2.124 ns) = 3.894 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'Q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "3.894 ns" { REGL[0] Q[0] } "NODE_NAME" } "" } } { "ADCINT.VHD" "" { Text "F:/zonghesheji/EXP/ADC/ADCINT.VHD" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 54.55 % ) " "Info: Total cell delay = 2.124 ns ( 54.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.770 ns ( 45.45 % ) " "Info: Total interconnect delay = 1.770 ns ( 45.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "3.894 ns" { REGL[0] Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.894 ns" { REGL[0] Q[0] } { 0.000ns 1.770ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "7.130 ns" { CLK current_state.st4 REGL[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.130 ns" { CLK CLK~out0 current_state.st4 REGL[0] } { 0.000ns 0.000ns 0.558ns 3.457ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ADCINT" "UNKNOWN" "V1" "F:/zonghesheji/EXP/ADC/db/ADCINT.quartus_db" { Floorplan "F:/zonghesheji/EXP/ADC/" "" "3.894 ns" { REGL[0] Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.894 ns" { REGL[0] Q[0] } { 0.000ns 1.770ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}