adcint.fit.eqn

用FPGA实现的ADC采样器

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--current_state.st1 is current_state.st1 at LC_X8_Y6_N6
--operation mode is normal

current_state.st1_lut_out = !current_state.st0;
current_state.st1 = DFFEAS(current_state.st1_lut_out, GLOBAL(CLK), VCC, , , , , , );


--current_state.st3 is current_state.st3 at LC_X8_Y6_N4
--operation mode is normal

current_state.st3_lut_out = EOC & current_state.st2;
current_state.st3 = DFFEAS(current_state.st3_lut_out, GLOBAL(CLK), VCC, , , , , , );


--A1L21 is OE~0 at LC_X8_Y6_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

current_state.st4_qfbk = current_state.st4;
A1L21 = current_state.st3 # current_state.st4_qfbk;

--current_state.st4 is current_state.st4 at LC_X8_Y6_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

current_state.st4 = DFFEAS(A1L21, GLOBAL(CLK), VCC, , , current_state.st3, , , VCC);


--REGL[0] is REGL[0] at LC_X7_Y1_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

REGL[0]_lut_out = GND;
REGL[0] = DFFEAS(REGL[0]_lut_out, GLOBAL(current_state.st4), VCC, , , D[0], , , VCC);


--REGL[1] is REGL[1] at LC_X26_Y8_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

REGL[1]_lut_out = GND;
REGL[1] = DFFEAS(REGL[1]_lut_out, GLOBAL(current_state.st4), VCC, , , D[1], , , VCC);


--REGL[2] is REGL[2] at LC_X6_Y13_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

REGL[2]_lut_out = GND;
REGL[2] = DFFEAS(REGL[2]_lut_out, GLOBAL(current_state.st4), VCC, , , D[2], , , VCC);


--REGL[3] is REGL[3] at LC_X16_Y13_N2
--operation mode is normal

REGL[3]_lut_out = D[3];
REGL[3] = DFFEAS(REGL[3]_lut_out, GLOBAL(current_state.st4), VCC, , , , , , );


--REGL[4] is REGL[4] at LC_X26_Y7_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

REGL[4]_lut_out = GND;
REGL[4] = DFFEAS(REGL[4]_lut_out, GLOBAL(current_state.st4), VCC, , , D[4], , , VCC);


--REGL[5] is REGL[5] at LC_X26_Y11_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

REGL[5]_lut_out = GND;
REGL[5] = DFFEAS(REGL[5]_lut_out, GLOBAL(current_state.st4), VCC, , , D[5], , , VCC);


--REGL[6] is REGL[6] at LC_X1_Y1_N2
--operation mode is normal

REGL[6]_lut_out = D[6];
REGL[6] = DFFEAS(REGL[6]_lut_out, GLOBAL(current_state.st4), VCC, , , , , , );


--REGL[7] is REGL[7] at LC_X24_Y13_N2
--operation mode is normal

REGL[7]_lut_out = D[7];
REGL[7] = DFFEAS(REGL[7]_lut_out, GLOBAL(current_state.st4), VCC, , , , , , );


--current_state.st0 is current_state.st0 at LC_X8_Y6_N5
--operation mode is normal

current_state.st0_lut_out = !current_state.st4;
current_state.st0 = DFFEAS(current_state.st0_lut_out, GLOBAL(CLK), VCC, , , , , , );


--current_state.st2 is current_state.st2 at LC_X8_Y6_N8
--operation mode is normal

current_state.st2_lut_out = current_state.st1 # !EOC & current_state.st2;
current_state.st2 = DFFEAS(current_state.st2_lut_out, GLOBAL(CLK), VCC, , , , , , );


--CLK is CLK at PIN_17
--operation mode is input

CLK = INPUT();


--EOC is EOC at PIN_49
--operation mode is input

EOC = INPUT();


--D[0] is D[0] at PIN_48
--operation mode is input

D[0] = INPUT();


--D[1] is D[1] at PIN_94
--operation mode is input

D[1] = INPUT();


--D[2] is D[2] at PIN_139
--operation mode is input

D[2] = INPUT();


--D[3] is D[3] at PIN_126
--operation mode is input

D[3] = INPUT();


--D[4] is D[4] at PIN_91
--operation mode is input

D[4] = INPUT();


--D[5] is D[5] at PIN_103
--operation mode is input

D[5] = INPUT();


--D[6] is D[6] at PIN_38
--operation mode is input

D[6] = INPUT();


--D[7] is D[7] at PIN_112
--operation mode is input

D[7] = INPUT();


--ALE is ALE at PIN_7
--operation mode is output

ALE = OUTPUT(current_state.st1);


--START is START at PIN_10
--operation mode is output

START = OUTPUT(current_state.st1);


--OE is OE at PIN_26
--operation mode is output

OE = OUTPUT(A1L21);


--ADDA is ADDA at PIN_40
--operation mode is output

ADDA = OUTPUT(VCC);


--LOCK0 is LOCK0 at PIN_11
--operation mode is output

LOCK0 = OUTPUT(current_state.st4);


--Q[0] is Q[0] at PIN_36
--operation mode is output

Q[0] = OUTPUT(REGL[0]);


--Q[1] is Q[1] at PIN_96
--operation mode is output

Q[1] = OUTPUT(REGL[1]);


--Q[2] is Q[2] at PIN_2
--operation mode is output

Q[2] = OUTPUT(REGL[2]);


--Q[3] is Q[3] at PIN_125
--operation mode is output

Q[3] = OUTPUT(REGL[3]);


--Q[4] is Q[4] at PIN_85
--operation mode is output

Q[4] = OUTPUT(REGL[4]);


--Q[5] is Q[5] at PIN_104
--operation mode is output

Q[5] = OUTPUT(REGL[5]);


--Q[6] is Q[6] at PIN_35
--operation mode is output

Q[6] = OUTPUT(REGL[6]);


--Q[7] is Q[7] at PIN_111
--operation mode is output

Q[7] = OUTPUT(REGL[7]);