adcint.tan.rpt

用FPGA实现的ADC采样器

+----------------------------------------------------------------------------+
; tco                                                                        ;
+-------+--------------+------------+-------------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From              ; To    ; From Clock ;
+-------+--------------+------------+-------------------+-------+------------+
; N/A   ; None         ; 11.248 ns  ; REGL[0]           ; Q[0]  ; CLK        ;
; N/A   ; None         ; 11.245 ns  ; REGL[2]           ; Q[2]  ; CLK        ;
; N/A   ; None         ; 10.812 ns  ; REGL[7]           ; Q[7]  ; CLK        ;
; N/A   ; None         ; 10.812 ns  ; REGL[3]           ; Q[3]  ; CLK        ;
; N/A   ; None         ; 10.672 ns  ; REGL[5]           ; Q[5]  ; CLK        ;
; N/A   ; None         ; 10.672 ns  ; REGL[4]           ; Q[4]  ; CLK        ;
; N/A   ; None         ; 10.672 ns  ; REGL[1]           ; Q[1]  ; CLK        ;
; N/A   ; None         ; 10.622 ns  ; REGL[6]           ; Q[6]  ; CLK        ;
; N/A   ; None         ; 8.183 ns   ; current_state.st3 ; OE    ; CLK        ;
; N/A   ; None         ; 7.722 ns   ; current_state.st1 ; START ; CLK        ;
; N/A   ; None         ; 7.722 ns   ; current_state.st1 ; ALE   ; CLK        ;
; N/A   ; None         ; 7.597 ns   ; current_state.st4 ; OE    ; CLK        ;
; N/A   ; None         ; 7.558 ns   ; current_state.st4 ; LOCK0 ; CLK        ;
+-------+--------------+------------+-------------------+-------+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To                ; To Clock ;
+---------------+-------------+-----------+------+-------------------+----------+
; N/A           ; None        ; 1.047 ns  ; D[5] ; REGL[5]           ; CLK      ;
; N/A           ; None        ; 1.047 ns  ; D[1] ; REGL[1]           ; CLK      ;
; N/A           ; None        ; 1.043 ns  ; D[4] ; REGL[4]           ; CLK      ;
; N/A           ; None        ; 0.570 ns  ; D[2] ; REGL[2]           ; CLK      ;
; N/A           ; None        ; 0.529 ns  ; D[0] ; REGL[0]           ; CLK      ;
; N/A           ; None        ; 0.411 ns  ; D[7] ; REGL[7]           ; CLK      ;
; N/A           ; None        ; 0.411 ns  ; D[3] ; REGL[3]           ; CLK      ;
; N/A           ; None        ; 0.356 ns  ; D[6] ; REGL[6]           ; CLK      ;
; N/A           ; None        ; -4.785 ns ; EOC  ; current_state.st2 ; CLK      ;
; N/A           ; None        ; -4.786 ns ; EOC  ; current_state.st3 ; CLK      ;
+---------------+-------------+-----------+------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Mon Dec 18 21:22:13 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ADCINT -c ADCINT --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "current_state.st4" as buffer
Info: Clock "CLK" Internal fmax is restricted to 275.03 MHz between source register "current_state.st2" and destination register "current_state.st2"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.040 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.st2'
            Info: 2: + IC(0.562 ns) + CELL(0.478 ns) = 1.040 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.st2'
            Info: Total cell delay = 0.478 ns ( 45.96 % )
            Info: Total interconnect delay = 0.562 ns ( 54.04 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.738 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'
                Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.st2'
                Info: Total cell delay = 2.180 ns ( 79.62 % )
                Info: Total interconnect delay = 0.558 ns ( 20.38 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.738 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'
                Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X8_Y6_N8; Fanout = 2; REG Node = 'current_state.st2'
                Info: Total cell delay = 2.180 ns ( 79.62 % )
                Info: Total interconnect delay = 0.558 ns ( 20.38 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "current_state.st3" (data pin = "EOC", clock pin = "CLK") is 4.838 ns
    Info: + Longest pin to register delay is 7.539 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_49; Fanout = 2; PIN Node = 'EOC'
        Info: 2: + IC(5.457 ns) + CELL(0.607 ns) = 7.539 ns; Loc. = LC_X8_Y6_N4; Fanout = 2; REG Node = 'current_state.st3'
        Info: Total cell delay = 2.082 ns ( 27.62 % )
        Info: Total interconnect delay = 5.457 ns ( 72.38 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.738 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(0.558 ns) + CELL(0.711 ns) = 2.738 ns; Loc. = LC_X8_Y6_N4; Fanout = 2; REG Node = 'current_state.st3'
        Info: Total cell delay = 2.180 ns ( 79.62 % )
        Info: Total interconnect delay = 0.558 ns ( 20.38 % )
Info: tco from clock "CLK" to destination pin "Q[0]" through register "REGL[0]" is 11.248 ns
    Info: + Longest clock path from clock "CLK" to source register is 7.130 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X8_Y6_N2; Fanout = 11; REG Node = 'current_state.st4'
        Info: 3: + IC(3.457 ns) + CELL(0.711 ns) = 7.130 ns; Loc. = LC_X7_Y1_N2; Fanout = 1; REG Node = 'REGL[0]'
        Info: Total cell delay = 3.115 ns ( 43.69 % )
        Info: Total interconnect delay = 4.015 ns ( 56.31 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.894 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y1_N2; Fanout = 1; REG Node = 'REGL[0]'
        Info: 2: + IC(1.770 ns) + CELL(2.124 ns) = 3.894 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'Q[0]'
        Info: Total cell delay = 2.124 ns ( 54.55 % )
        Info: Total interconnect delay = 1.770 ns ( 45.45 % )
Info: th for register "REGL[5]" (data pin = "D[5]", clock pin = "CLK") is 1.047 ns
    Info: + Longest clock path from clock "CLK" to destination register is 7.183 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'CLK'
        Info: 2: + IC(0.558 ns) + CELL(0.935 ns) = 2.962 ns; Loc. = LC_X8_Y6_N2; Fanout = 11; REG Node = 'current_state.st4'
        Info: 3: + IC(3.510 ns) + CELL(0.711 ns) = 7.183 ns; Loc. = LC_X26_Y11_N2; Fanout = 1; REG Node = 'REGL[5]'
        Info: Total cell delay = 3.115 ns ( 43.37 % )
        Info: Total interconnect delay = 4.068 ns ( 56.63 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.151 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_103; Fanout = 1; PIN Node = 'D[5]'
        Info: 2: + IC(4.567 ns) + CELL(0.115 ns) = 6.151 ns; Loc. = LC_X26_Y11_N2; Fanout = 1; REG Node = 'REGL[5]'
        Info: Total cell delay = 1.584 ns ( 25.75 % )
        Info: Total interconnect delay = 4.567 ns ( 74.25 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Mon Dec 18 21:22:13 2006
    Info: Elapsed time: 00:00:01