adc0809.vhd

ADC0809的驱动程序

library ieee;--本文件是ADC0809的驱动程序，其中由软件循环从8个端口获得转换数据，时间可以由软
use ieee.std_logic_1164.all;--件程序调节，输出完全是ADC0809的时序，经仿真正确！并下载到FPGA
use ieee.std_logic_unsigned.all;--中验证,正确!
entity adc0809 is--实体定义
port(
reset : in std_logic;
clk : in std_logic;
eoc : in std_logic;

lock : out std_logic;
ale : out std_logic;
start : out std_logic;
oe : out std_logic;
-- st : out integer range 7 downto 0;
adda : out std_logic_vector( 2 downto 0));
end entity;
architecture func of adc0809 is
type state_type is (st0, st1, st2, st3, st4, st5, st6);--信号定义
signal current_state,next_state : state_type:=st0;
signal lock1 : std_logic;
signal reg : std_logic_vector(7 downto 0);
signal clk1:std_logic;
signal qq:std_logic_vector(22 downto 0);
begin
clock:process(clk)                 --对系统时钟进行分频,用以控制循环的频率
begin
 if clk'event and clk='1' then qq<=qq+1;              
if qq<"01111111111111111111111" THEN clk1<='1';
  elsif qq>="01111111111111111111111" then clk1<='0';	
    end if;  
end if;
end process;
process(clk1)--循环从8个端口获得数据
variable d :integer range 0 to 7;
begin
if clk1'event and clk1='1' then
case d is
when 0=>adda<="000" ;
d:=1;
when 1=>adda <="001" ;
d:=2;
when 2=>adda <="010" ;
d:=3;
when 3=>adda <="011" ;
d:=4;
when 4=>adda<="100" ;
d:=5;
when 5=>adda <="101" ;
d:=6;
when 6=>adda<="110" ;
d:=7;
when 7=>adda <="111" ;
d:=0;
end case;
end if;
end process;
lock<=lock1;
process (current_state, eoc) --状态机的描述
begin
case current_state is
when st0=>
ale<='0';
start<='0';
oe<='0';
lock1<='0';
next_state<=st1;
when st1=>
ale<='1';
start<='0';
oe<='0';
lock1<='0';
next_state<=st2;
when st2=>
ale<='0';
start<='1';
oe<='0';
lock1<='0';
next_state<=st3;
when st3=>
ale<='0';
start<='0';
oe<='0';
lock1<='0';
if(eoc='0')then
next_state<=st4;
else
next_state<=st3;
end if;
when st4=>
ale<='0';
start<='0';
oe<='0';
lock1<='0';
if(eoc='1')then
next_state<=st5;
else
next_state<=st4;
end if; 
when st5=>
ale<='0';
start<='0';
oe<='1';
lock1<='0';
next_state<=st6; 
when st6=>
ale<='0';
start<='0';
oe<='1';
lock1<='1';
next_state<=st0;
when others=>
next_state<=st0;
end case;
end process;
process (clk,reset)
begin
if(reset='1')then
current_state<=st0;
elsif (clk'event and clk='1') then
current_state<=next_state;
end if;
end process;
end func;