watchgai.map.qmsg

来自「利用FPGA的V4开发板制作的电子表」· QMSG 代码 · 共 52 行 · 第 1/3 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 07 15:57:48 2008 " "Info: Processing started: Wed May 07 15:57:48 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off watchgai -c watchgai " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off watchgai -c watchgai" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "watchgai.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file watchgai.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 watchgai-jishu " "Info: Found design unit 1: watchgai-jishu" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 33 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 watchgai " "Info: Found entity 1: watchgai" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "biaogai.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file biaogai.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 biaogai " "Info: Found entity 1: biaogai" {  } { { "biaogai.bdf" "" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "biaogai " "Info: Elaborating entity \"biaogai\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "watchgai watchgai:inst6 " "Info: Elaborating entity \"watchgai\" for hierarchy \"watchgai:inst6\"" {  } { { "biaogai.bdf" "inst6" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { { 144 272 408 272 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "beef watchgai.vhd(38) " "Warning (10541): VHDL Signal Declaration warning at watchgai.vhd(38): used implicit default value for signal \"beef\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 38 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "ma watchgai.vhd(51) " "Info (10035): Verilog HDL or VHDL information at watchgai.vhd(51): object \"ma\" declared but not used" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 51 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "fa watchgai.vhd(51) " "Info (10035): Verilog HDL or VHDL information at watchgai.vhd(51): object \"fa\" declared but not used" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 51 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "sa watchgai.vhd(51) " "Info (10035): Verilog HDL or VHDL information at watchgai.vhd(51): object \"sa\" declared but not used" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 51 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk_temp watchgai.vhd(79) " "Warning (10492): VHDL Process Statement warning at watchgai.vhd(79): signal \"clk_temp\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 79 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "miao watchgai.vhd(127) " "Warning (10492): VHDL Process Statement warning at watchgai.vhd(127): signal \"miao\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 127 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "fen watchgai.vhd(435) " "Warning (10492): VHDL Process Statement warning at watchgai.vhd(435): signal \"fen\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 435 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "shi watchgai.vhd(741) " "Warning (10492): VHDL Process Statement warning at watchgai.vhd(741): signal \"shi\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 741 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "p4 watchgai.vhd(77) " "Warning (10631): VHDL Process Statement warning at watchgai.vhd(77): signal or variable \"p4\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"p4\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "watchgai.vhd" "" { Text "E:/project/FPGA/project1/watchgai/watchgai.vhd" 77 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus51/libraries/megafunctions/sld_signaltap.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_signaltap_pack " "Info: Found design unit 1: sld_signaltap_pack" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" 62 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_signaltap-rtl " "Info: Found design unit 2: sld_signaltap-rtl" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" 170 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_signaltap " "Info: Found entity 1: sld_signaltap" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" 85 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd 14 7 " "Info: Found 14 design units, including 7 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_ela_control-rtl " "Info: Found design unit 1: sld_ela_control-rtl" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 118 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_ela_level_seq_mgr-rtl " "Info: Found design unit 2: sld_ela_level_seq_mgr-rtl" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 844 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_ela_state_machine-rtl " "Info: Found design unit 3: sld_ela_state_machine-rtl" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1022 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_ela_seg_state_machine-rtl " "Info: Found design unit 4: sld_ela_seg_state_machine-rtl" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1125 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 sld_ela_post_trigger_counter-rtl " "Info: Found design unit 5: sld_ela_post_trigger_counter-rtl" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1215 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "6 sld_ela_segment_mgr-rtl " "Info: Found design unit 6: sld_ela_segment_mgr-rtl" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1342 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "7 sld_ela_basic_multi_level_trigger-rtl " "Info: Found design unit 7: sld_ela_basic_multi_level_trigger-rtl" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1521 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_ela_control " "Info: Found entity 1: sld_ela_control" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 67 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_ela_level_seq_mgr " "Info: Found entity 2: sld_ela_level_seq_mgr" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 817 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 sld_ela_state_machine " "Info: Found entity 3: sld_ela_state_machine" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1000 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 sld_ela_seg_state_machine " "Info: Found entity 4: sld_ela_seg_state_machine" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1105 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 sld_ela_post_trigger_counter " "Info: Found entity 5: sld_ela_post_trigger_counter" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1195 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 sld_ela_segment_mgr " "Info: Found entity 6: sld_ela_segment_mgr" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1319 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 sld_ela_basic_multi_level_trigger " "Info: Found entity 7: sld_ela_basic_multi_level_trigger" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_ela_control.vhd" 1487 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}