watchgai.map.qmsg

来自「利用FPGA的V4开发板制作的电子表」· QMSG 代码 · 共 52 行 · 第 1/3 页

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus51/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "lpm_shiftreg.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_shiftreg.tdf" 37 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mbpmg-rtl " "Info: Found design unit 1: sld_mbpmg-rtl" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" 65 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_sbpmg-rtl " "Info: Found design unit 2: sld_sbpmg-rtl" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" 293 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mbpmg " "Info: Found entity 1: sld_mbpmg" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" 44 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_sbpmg " "Info: Found entity 2: sld_sbpmg" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_mbpmg.vhd" 272 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus51/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_7jc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_7jc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_7jc " "Info: Found entity 1: cntr_7jc" {  } { { "db/cntr_7jc.tdf" "" { Text "E:/project/FPGA/project1/watchgai/db/cntr_7jc.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_6sb.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_6sb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_6sb " "Info: Found entity 1: cntr_6sb" {  } { { "db/cntr_6sb.tdf" "" { Text "E:/project/FPGA/project1/watchgai/db/cntr_6sb.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus51/libraries/megafunctions/lpm_compare.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/lpm_compare.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_compare " "Info: Found entity 1: lpm_compare" {  } { { "lpm_compare.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_compare.tdf" 264 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_nth.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_nth.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_nth " "Info: Found entity 1: cmpr_nth" {  } { { "db/cmpr_nth.tdf" "" { Text "E:/project/FPGA/project1/watchgai/db/cmpr_nth.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_acquisition_buffer-rtl " "Info: Found design unit 1: sld_acquisition_buffer-rtl" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" 73 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_offload_buffer_mgr-rtl " "Info: Found design unit 2: sld_offload_buffer_mgr-rtl" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" 308 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_acquisition_buffer " "Info: Found entity 1: sld_acquisition_buffer" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" 46 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_offload_buffer_mgr " "Info: Found entity 2: sld_offload_buffer_mgr" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" 271 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_smd.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_smd.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_smd " "Info: Found entity 1: cntr_smd" {  } { { "db/cntr_smd.tdf" "" { Text "E:/project/FPGA/project1/watchgai/db/cntr_smd.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus51/libraries/megafunctions/lpm_ff.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/lpm_ff.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ff " "Info: Found entity 1: lpm_ff" {  } { { "lpm_ff.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_ff.tdf" 46 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_hlb2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hlb2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_hlb2 " "Info: Found entity 1: altsyncram_hlb2" {  } { { "db/altsyncram_hlb2.tdf" "" { Text "E:/project/FPGA/project1/watchgai/db/altsyncram_hlb2.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_igb.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_igb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_igb " "Info: Found entity 1: cntr_igb" {  } { { "db/cntr_igb.tdf" "" { Text "E:/project/FPGA/project1/watchgai/db/cntr_igb.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Info: Analysis and Synthesis generated SignalTap II or debug node instance \"auto_signaltap_0\"" { { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|biaogai\|clk acq_clk " "Info: Source node \"\|biaogai\|clk\" connects to port \"acq_clk\"" {  } { { "biaogai.bdf" "clk" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { { 288 32 200 304 "clk" "" } } } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|biaogai\|data\[0\] acq_trigger_in\[0\] " "Info: Source node \"\|biaogai\|data\[0\]\" connects to port \"acq_trigger_in\[0\]\"" {  } { { "biaogai.bdf" "data\[0\]" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { { 112 464 640 128 "data\[7..0\]" "" } } } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|biaogai\|data\[0\] acq_data_in\[0\] " "Info: Source node \"\|biaogai\|data\[0\]\" connects to port \"acq_data_in\[0\]\"" {  } { { "biaogai.bdf" "data\[0\]" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { { 112 464 640 128 "data\[7..0\]" "" } } } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|biaogai\|data\[1\] acq_trigger_in\[1\] " "Info: Source node \"\|biaogai\|data\[1\]\" connects to port \"acq_trigger_in\[1\]\"" {  } { { "biaogai.bdf" "data\[1\]" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { { 112 464 640 128 "data\[7..0\]" "" } } } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|biaogai\|data\[1\] acq_data_in\[1\] " "Info: Source node \"\|biaogai\|data\[1\]\" connects to port \"acq_data_in\[1\]\"" {  } { { "biaogai.bdf" "data\[1\]" { Schematic "E:/project/FPGA/project1/watchgai/biaogai.bdf" { { 112 464 640 128 "data\[7..0\]" "" } } } }  } 0 0 "Source node \"%1!s!\" connects to port \"%2!s!\"" 0 0}  } {  } 0 0 "Analysis and Synthesis generated SignalTap II or debug node instance \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 167 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1127 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "../../../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "E:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1112 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus51/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "e:/altera/quartus51/libraries/megafunctions/lpm_decode.tdf" 62 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_rpe.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_rpe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_rpe " "Info: Found entity 1: decode_rpe" {  } { { "db/decode_rpe.tdf" "" { Text "E:/project/FPGA/project1/watchgai/db/decode_rpe.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}