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来自「一个关于热敏打印机时序的仿真程序,能够应用于大多数的热敏打印机中,实现了打印数据」· 代码 · 共 173 行

# Reading C:/Modeltech_6.1f/tcl/vsim/pref.tcl 
#  OpenFile "C:/Phoenix/verilog/PTOS/WORK/PTOS.mpf" 
# Loading project PTOS
# Compile of Paralla to serials.v was successful.
# Compile of test.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim
# Compile of Paralla to serials.v was successful.
# Compile of test.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim
# Compile of Paralla to serials.v was successful.
# Compile of test.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim
# Compile of Paralla to serials.v was successful.
# Compile of test.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim
# Compile of Paralla to serials.v was successful.
# Compile of test.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim
# Compile of Paralla to serials.v was successful.
# Compile of test.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim
# Compile of Paralla to serials.v was successful.
# Compile of test.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim
# Compile of Paralla to serials.v was successful.
# Compile of test.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim
# Compile of Paralla to serials.v was successful.
# Compile of test.v was successful.
# 2 compiles, 0 failed with no errors. 
# Compile of Paralla to serials.v was successful.
# Compile of test.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim
# Compile of Paralla to serials.v was successful.
# Compile of test.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim
# Compile of Paralla to serials.v was successful.
# Compile of test.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim -coverage work.test
# vsim -coverage work.test 
# Loading work.test
# Loading work.PtoS
quit -sim
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim
vsim work.test
# vsim work.test 
# Loading work.test
# Loading work.PtoS
add wave sim:/test/u0/*
run -all
# Break at C:/Phoenix/verilog/PTOS/TB/test.v line 74
quit -sim