top.mrp

Verilog编程

Release 6.1i Map G.26
Xilinx Mapping Report File for Design 'top'

Design Information
------------------
Command Line   : D:/Xilinx/bin/nt/map.exe -intstyle ise -p xc3s400-pq208-4 -cm
area -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd top.pcf 
Target Device  : x3s400
Target Package : pq208
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.16 $
Mapped Date    : Thu May 08 16:23:12 2008

Design Summary
--------------
Number of errors:      0
Number of warnings:   18
Logic Utilization:
  Number of Slice Flip Flops:       1,554 out of   7,168   21%
  Number of 4 input LUTs:           1,030 out of   7,168   14%
Logic Distribution:
  Number of occupied Slices:                        1,140 out of   3,584   31%
    Number of Slices containing only related logic:   1,140 out of   1,140  100%
    Number of Slices containing unrelated logic:          0 out of   1,140    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,120 out of   7,168   15%
  Number used as logic:              1,030
  Number used as a route-thru:          90
  Number of bonded IOBs:               97 out of     141   68%
  Number of Block RAMs:                6 out of      16   37%
  Number of MULT18X18s:                6 out of      16   37%
  Number of GCLKs:                     3 out of       8   37%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  447,247
Additional JTAG gate count for IOBs:  4,656
Peak Memory Usage:  89 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT - Resistive elements (PULLUP/PULLDOWN/KEEPER) on Clock net driving
   IBUFG symbol "NWE_n_BUFGP/IBUFG" (output signal=NWE_n_BUFGP/IBUFG) will be
   ignored.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<10> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<0> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<1> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<2> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<3> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<4> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<5> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<6> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<7> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<8> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   SINE2<9> is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   clk_out1 is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   clk_out2 is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   clk_out3 is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   clk_out4 is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   clk_out5 is set but TMUX is not configured.
WARNING:DesignRules:334 - Blockcheck: PULL on an active net. PULL of comp
   clk_out6 is set but TMUX is not configured.

Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "NWE_n_BUFGP" (output signal=NWE_n_BUFGP),
   BUFG symbol "instance_name_CLK0_BUFG_INST" (output signal=CLK0),
   BUFG symbol "instance_name_CLKFX_BUFG_INST" (output signal=CLKDV_OUT)
INFO:DesignRules:547 - Blockcheck: To achieve optimal frequency synthesis
   performance with the CLKFX and CLKFX180 outputs of the DCM comp
   instance_name_DCM_INST, consult the Virtex-II Interactive Data Sheet.

Section 4 - Removed Logic Summary
---------------------------------
   7 block(s) removed
   8 block(s) optimized away
   1 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

Loadless block "instance_name_CLK180_BUFG_INST" (CKBUF) removed.
 The signal "instance_name_CLK180_BUF" is loadless and has been removed.
Unused block "my_dds4_DDS10_rom/VCC" (ONE) removed.
Unused block "my_dds4_DDS20_rom/VCC" (ONE) removed.
Unused block "my_dds4_DDS30_rom/VCC" (ONE) removed.
Unused block "my_dds4_DDS40_rom/VCC" (ONE) removed.
Unused block "my_dds4_DDS50_rom/VCC" (ONE) removed.
Unused block "my_dds4_DDS60_rom/VCC" (ONE) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC
GND 		my_dds4_DDS10_rom/GND
GND 		my_dds4_DDS20_rom/GND
GND 		my_dds4_DDS30_rom/GND
GND 		my_dds4_DDS40_rom/GND
GND 		my_dds4_DDS50_rom/GND
GND 		my_dds4_DDS60_rom/GND

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+